ANAHEIM, CA At the Design Automation Conference here key thought leaders in the area of 3-D packaging made an attempt to forecast a roadmap for 3-D thru silicon vias interconnects.
The consensus of the first ever panel discussion dedicated to TSVs at a DAC is that it will be awhile but it is inevitable that TSVs need to be phased in as a technology for obtaining performance levels needed by a host of applications.
"3-D technology will hit the market in the next two to three years, said Pol Marchal, a principal scientist at IMEC. "The technology has great benefits for the three main application drivers of the semiconductor industry: convergence, high performance and memory systems."
Marchal said that IMEC has road maps for the design and technology challenges for each of the application domains. For the challenges to be met, "EDA must contribute an integrated design flow enabling the co-optimization of chip and package design for signal integrity and power integrity, as well as mechanical/thermal integrity," said Marchal.
"3-D IC integration using TSV interconnections is becoming a critical component to overcome the technology scaling barriers and low power requirements in mobile devices," said CAE researcher Myung-Soo Jang, of Samsung Electronics. In his presentation Jang showed an example of how with today's IC technology online video applications in 3-D and mobile apps will require as much as 12.8 Gbytes/s between I/O and memory. 3-D packaging technology can evetually lower that frequnecy by as much as by 8X in Samsung DDRs.
LC Lu, director of TSV technologies at Taiwan Semiconductors Manufacturing Co., predicted that "3-D IC/TSV is an industry trend gaining momentum due to the ever-converging alignment of the technology’s benefits for 'More than Moore' system-on-chip applications." Products using this technology will be rolled out in many different market segments.
TSMC recently extened its Open Inovation Platform with its Reference Flow 11.0 that emphasizes solutions provided by TSV technologies."Innovation is needed in good die sorting, multiple process variations, and thermal/mechanical stress," according to Lu.
"This is not a one size fits all applications type of technology", said Riko Radojcic, Director of Through Silicon Stacking Initiatives at Qualcomm. "It is all about managing new choices when making the decision to go with TSV technology." Radojcic said that it is essential to implement a Path Finding process up front in the system design in order to explore design options and make the right choices related to technology, costs and die interactions.
In addition Radojcic said that at the manufaturing end designers need to implement a "physical space exploration" Qualcomm calls Tech Tuning in order to manage thermal and mechnical stress of TVS interconnects. "Our goal in our partnership with IMEC and AutoESL is to come up with an exploratory design flow,"said Radojcic.
"This will be a graceful evolution from our known 2-D world to the TVS world in 3-D, where the 'Four Horsemen of Apocaplypse--design, thermal, test, and cost' will be tamed into four working horses plowing our new 3-D field, " according to Radojcic.
"It is our 'man on the moon' project with a long gestation period," said IMEC's Marshal.
Joe Adam, a principle of of JMA Consulting predicted that TSV adoption will follow a simlar curve laid out by the mature system-in-chip technology. "From personal experience the SIP adoption rate for a mobile device by Conexant/IBM followed a typical S-curve of first adopter, second adopter, second sources, and multiple sockets in 7 to 8 years," said Adam. "I expect this will be similar with 3-D TSVs."
Moderator Andrew Yang, co-founder and CEO of Apache Design Solutions, said it best: "Two years ago, the big unceasing question was "Why 3D?" Today, the questions are "When 3D?" and "How 3D?"
The TSV panelists represent "a few brave souls who have taken this disruptive interconnect technology and are investing in it today to gain benefit from it tomorrow" said Yang. "The needed EDA tools will follow."