Thame, UK - Imperas, source for instruction accurate processor modeling and simulation through the Open Virtual Platforms (OVP) initiative, has released fast models of PowerPC processors. These models work with the OVP simulator, OVPsim, where they have shown performance reaching over one thousand million instructions per second (MIPS). The models are free and available as open source from the OVP website.
The addition of the models of the PowerPC cores brings OVP to nearly 50 different models of processor cores, all running at very high speed, and all working with both the OVP and Imperas simulators. All OVP processor models are instruction accurate and focused on enabling embedded software developers to have a development environment available early to accelerate the software development cycle.
Virtual platforms utilizing these OVP processor models can be created with the OVP peripheral and platform models, or the processor models can be integrated into SystemC/TLM-2.0 based virtual platforms using the TLM-2.0 interface available with all OVP processor models.
In addition to working with the OVP simulator, these models work with the Imperas advanced tools for multicore software verification, analysis and debug, including key tools for software development on virtual platforms, such as OS and CPU-aware tracing, profiling code analysis, and multicore debug.
For more information visit www.Imperas.com.
Fast Instruction Accurate models are available from the OVP website for MIPS, ARM, Virage ARC, NEC v850, Power Architecture, OpenCores, SPARC and other processor families. For more information about the Open Virtual Platforms Initiative visit www.OVPworld.org.