SANTA CLARA, Calif. — After a false start to forge a new mobile DRAM interface technology, a consortium has regrouped and redefined its specification.
The Serial Port Memory Technology Consortium (SPMT) recently scrapped its original, serial charter to endorse a hybrid parallel/serial approach. SPMT also claims that it has a new and major benefactor that will help disrupt the market. Marvell Technology Group Ltd. recently joined the fold and provided key input for the new specification, which combines existing parallel and serial technology in mobile DRAMs.
But is that enough to propel SPMT? And will the effort fizzle—again?
In any case, there is a need for a new solution. Current mobile systems use mobile DDR interface technology. Now, to boost memory bandwidth, a new mobile interface technology called LPDDR2 is ramping up. Going beyond LPDDR2, vendors claim that a new technology is required.
Besides SPMT, other rival efforts in the arena include MIPI and Rambus’ XDR, among others. All of them anticipate a problem in smartphones and other mobile systems. In the distant future, 3-D devices based on through-silicon-vias (TSVs) may be required in such systems.
In terms of bandwidth, LPDDR2 already "is hitting the wall,’’ Jim Venable, president of SPMT, said at a press event here on Tuesday (July 27).
"We can live with what we have for another year," said Sehat Sutardja, chairman, president and chief executive at Marvell, but "there are serious limitations in the (LPDDR2) memory interface. We are running out of pins."
As a result, a new solution is required for smartphones and other devices, Rob Dhat, director of strategic development at Rambus Inc., said at the Memcon conference here on Wednesday (July 28). By 2012 or so, there is a need for a solution that has "two to three times" more bandwidth, he said.
Rambus claims it has the best solution.
Meanwhile, after falling on its face the first time around—and perhaps falling behind its rivals—the SPMT group claims to be on the right track to solve the problem. Silicon Image Inc., for one, is banking on it; SPMT is a subsidiary of Silicon Image.
In 2008, ARM, Ericsson, Hynix, LG, Silicon Image, Samsung, Sony Ericsson Mobile and STMicroelectronics formed a new working group in the mobile DRAM space. Led by Silicon Image, SPMT hoped to establish a high-speed, multiport serial interface for DRAMs used in mobile apps. The market was expected to see a new class of serial DRAMs, dubbed SPDRAMs.
In theory, serial DRAMs made sense, as memory bandwidth in mobile devices are said to be hitting the wall. SPDRAM was also supposed to reduce pin count and lower power consumption.
The trouble with serial DRAM? The market didn’t buy it. Current DRAMs in the mobile space utilize a parallel interface technology. Many OEMs are comfortable with today’s parallel technology, notably LPDDR2.
OEMs were generally reluctant to jump on a serial technology. Right or wrong, there is a perception that serial DRAM is too difficult to design in systems and consumes too much power. And DRAM makers were unwilling to put a technology into production that would not generate a return.
Suddenly, SPMT had a promising technology, but the group was headed toward a dead end. Then, thanks to several forces, SPMT revamped its efforts and changed direction, perhaps for the better.
In the first move, Silicon Image shook up its management, which changed the dynamics at SPMT. In January, Silicon Image announced the appointment of Camillo Martino as its new chief executive.
Martino made a startling conclusion: SPMT "was not going as fast as I would have liked," he told EE Times during a press event at Marvell’s headquarters here Tuesday. So, "we had to look at ourselves in the mirror."
Then, SPMT made two critical decisions, which have pointed the group in the right direction. "It’s back on track," he said.
In another major move, the group recently recruited one mover and shaker—Marvell—which may have saved the day for the group. "We provided a lot of input" in SPMT, said Marvell’s Sutardja.
Other SPMT members include ARM, Hynix, LG Electronics, Samsung Electronics and Silicon Image. Missing from the group are some original members, including Ericsson, Sony Ericsson Mobile and STMicroelectronics.
Others are also missing, namely members of MIPI. Intel, Motorola, Nokia, Samsung, STMicroelectronics and Texas Instruments are the current board members that lead that organization.
In June, SPMT dropped its previous specification and announced a new specification based on so-called SerialSwitch technology. Said to combine the best of parallel and serial technology, SerialSwitch reportedly delivers four times the bandwidth, pin for pin, at half the power of existing memory solutions, and offers a low-cost migration from parallel to serial memories.
A key is that the technology is backward-compatible with existing LPDDR2. "SerialSwitch technology has the low startup latency and low power of an LPDDR2 parallel interface at low bandwidths, and the low pin count, high performance and low power of serial technology at high bandwidths," according to SPMT.
The technology operates in legacy LPDDR2 mode with up to 1.6 GB/second in parallel mode. It is said to switch into overdrive in serial mode with up to 6.4 GB/s of bandwidth per channel.
The technology is optimized for mobile and consumer electronics applications with high-bandwidth requirements, such as HD video, 3-D action gaming and mobile projection, according to the group.
The first SPMT-based devices, namely DRAMs equipped with the technology, are expected to sample in the second half of 2011. End user products are expected in 2012. SPMT’s Venable denied that the group lags its rivals after having ditched its serial charter. He said the SPMT-based device timetable is roughly the same as the company’s previous schedule for SPDRAMs.
Others want product sooner rather than later. "We’d like to see samples of products come a lot sooner," Marvell’s Sutardja said.
LPDDR2 is said to run at a maximum of 4.3 GB/s, but there is a thirst for more bandwidth, Sutardja said, adding that "dual-channel [LPDDR2] is the end" of the road for the technology.
"We also can see [SPMT-based devices] used in every product," he said. Asked why SPMT will succeed this time around, he said, "SPMT has an advantage. It’s backward-compatible to LPDDR2."
Like Silicon Image, Marvell was a big proponent of serial DRAM interfaces and attempted to develop the technology in-house. Marvell attempted to generate interest in this technology, but it also ran into some resistance.
So Marvell decided to join SPMT. At present, there is a proposal to make the technology a Jedec standard. In fact, there are two new proposals on the table: SPMT and an ultrawide memory technology.
The ultrawide proposal calls for a technology with some 2,000 pins running at low frequency. "That’s crazy," said Marvell’s CEO, saying that the technology is like putting 1,000 bicycles on a high-speed freeway.
Other approaches are also vying for dominance in the market. Rambus’ Mobile XDR is capable of achieving data rates of 3.2 to 4.3 GB/s and is suited for next-generation smartphones, netbooks, and mobile gaming and multimedia products.
MIPI is also in the game, but the group has recently been quiet.