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IEDM to feature 3-D chips, carbon nanotubes, FinFETs

9/20/2010 09:23 PM EDT
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docdivakar
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re: IEDM to feature 3-D chips, carbon nanotubes, FinFETs
docdivakar   9/24/2010 3:06:43 AM
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Mark, nice summary, I am looking forward to IEDM in December. At 4um, the TSV that the Universitie de Savoie tried perhaps represents the state-of-the art by today's standards (I have seen results of some 5um study). So if there is coupling with adjacent 65-nm NMOS transistors and smaller TSV's, it clearly shows that one needs to start modeling TSV's as devices and understand their behavior. There may not be enough real estate to guard the victim transistors. Gobbling up more real estate is one of the problems TSV's face as is, so the problem you describe is screaming for more research to understand their behavior. Just curious, how does one go about getting advance copies of presentations in upcoming conferences? You mind sharing? :-) MP Divakar

Kinnar
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re: IEDM to feature 3-D chips, carbon nanotubes, FinFETs
Kinnar   9/21/2010 7:21:18 AM
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The IEEE International Electron Devices Meeting (IEDM) will be revolutionary meet, as the abstracts of the papers being presented at the event are very much innovative and some are related with nanotechnology. 3D chip is also something very required by the industries due to multiple core processors, this 3D technology will help reducing the chip size in a planar area.

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