SAN JOSE, Calif. - The IEEE International Electron Devices Meeting (IEDM) is almost here.
At the event, look for papers on 3-D chips, carbon nanotubes, FinFETs, MEMS, NAND and other topics. The event will be held in San Francisco from Dec. 6-8. Here's a sample of the papers:
On the logic side, TSMC will unveil a 22-/20-nm CMOS technology. It features FinFET transistor architectures, 193-nm immersion lithography, SiGe stressors, metal gates and high-k dielectrics. The FinFETs are built with dual-epitaxy and multiple stressors.
N-/P-channel on-current is 1200/1100µA/µm respectively, while off-current for both N and P versions is 100nA/µm, according to TSMC. The researchers used the new technology to build a dense 0.1µm2 SRAM memory cell, which had noise characteristics (90mV noise margin) even at a low 0.45V operating voltage, according to the silicon foundry giant.
In a competing technology, a team led by CEA LETI in France will say it grew double- and triple-walled carbon nanotubes with 4-5-nm diameters using a root-growth process. The work represents a significant step toward implementation of carbon nanotube vias, according to the group.
3-D chip design appears to be a theme as well. Through-silicon vias (TSVs) are holes running vertically through the stack, filled with metal that interconnects all the levels. At the IEDM, a team led by Universitie de Savoie in France will report that although 4µm-wide copper TSVs did electrically couple with adjacent 65-nm NMOS transistors to produce a spike in static drain current, no variation in their operation in a test circuit (a ring oscillator) was seen.
In another logic effort, a team led by University of Tokyo will announce an InGaAs MOSFET built on an insulating substrate, and also the thinnest InGaAs MOSFET ever made, with a 3.5-nm channel. Nonconducting substrates are key to the eventual integration of such devices with silicon CMOS architectures because they reduce short-channel effects.
On the memory front, researchers from Intel Corp. and Micron Technology Inc. will talk about a 25-nm 64-Gbit multi-level cell (MLC) NAND memory, with a small cell size of 0.0028µm2. The half-pitch of the cell is 24.5-nm in the word line direction and 28.5-nm in the bit line direction.
In MEMS, University of Denver researchers will describe a fully micromechanical oscillator that makes use of inter-related piezoresistive, thermal and mechanical effects to render it capable of self-sustained oscillation without the need for supporting electronic circuitry, whether under vacuum or in atmospheric pressure. The oscillators are capable of achieving frequencies as high as 6.6MHz, consume only milliwatts of power, achieve output voltage amplitude as high as 825mV, and consist of simple-to-fabricate silicon structures.
And not to be outdone, a paper from Purdue will describe the modeling and simulation of nanoscale devices with the goal of producing a low-cost, high-throughput lab-on-a-chip to detect DNA, proteins and other electrically charged biomolecules in blood and other electrolyte solutions.
Mark, nice summary, I am looking forward to IEDM in December. At 4um, the TSV that the Universitie de Savoie tried perhaps represents the state-of-the art by today's standards (I have seen results of some 5um study). So if there is coupling with adjacent 65-nm NMOS transistors and smaller TSV's, it clearly shows that one needs to start modeling TSV's as devices and understand their behavior. There may not be enough real estate to guard the victim transistors. Gobbling up more real estate is one of the problems TSV's face as is, so the problem you describe is screaming for more research to understand their behavior.
Just curious, how does one go about getting advance copies of presentations in upcoming conferences? You mind sharing? :-)
The IEEE International Electron Devices Meeting (IEDM) will be revolutionary meet, as the abstracts of the papers being presented at the event are very much innovative and some are related with nanotechnology.
3D chip is also something very required by the industries due to multiple core processors, this 3D technology will help reducing the chip size in a planar area.
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