LONDON Ė A European collaborative
research project has spent 2.5 years and 4.45 million euro (about $5.8
million) performing a characterization of an ARM926 core for the
statistical variability that is inherent at the 32-nm manufacturing
The project, called Reality for
short and "Reliable and variability tolerant system-on-a-chip design in
more-moore technologies" in full, was set up in 2008 to address issues
around design for variability, which becomes increasingly significant at
geometries below 32-nm.
The Reality project was led by
research institute IMEC (Leuven, Belgium) and included ARM,
STMicroelectronics, and the universities of Bologna, Glasgow and
Katholiek University Leuven. The participants received 2.9 million euro
(about $3.8 million) of tax-payers' funds from the European Commission.
The challenges taken on include
benchmarking the impact of the latest 32-nm CMOS process manufacturing
variability at all abstraction levels, from device to system-on-a-chip
level, while developing approaches to compensate for the negative impact
in the design of final products.
The work includes the 3-D
simulation of the statistical variability associated with metal gate
granularity and the corresponding metal work function variations have
been carried out to clarify the magnitude of statistical variability in
32-nm CMOS transistors with high-k/metal gate stack. At these dimensions
the metal granularities can double the variability if the metal grain
size becomes comparable to the transistor dimensions, the partners have
With regard to the ARM926 core the
correlation between the timing, leakage and dynamic power has been
demonstrated within die and on die-to-die variations.
Using the ARM core as a driver,
Reality has confirmed that the SRAM components are responsible for more
than the half of the variations on critical path timing. Hence,
Statistical Timing Analysis (STA) flows that assume predictable timing
response from these components may lead to over-optimistic conclusions.
To address this Reality has created a statistical characterization flow
including SRAM analysis.
With a novel flow integrating
manufacturing variations and the ageing effects for mixed-signal
circuits, the Reality project went further and developed a CAD
environment that allows designers to make more accurate estimations and
thus make circuits more energy and cost efficient, IMEC said in a
Reality also evaluated the impact
of process variation using software-level metrics and has demonstrated
that process variability should be a concern for software writers as
well as hardware designers. Variability will affect the performance of
multi-core multimedia platforms making it hard to guarantee
quality-of-service when running an application.
The partners have looked at
different design techniques as a way of mitigating that performance
variability, including Adaptive Body Biasing (ABB). Reality has shown
that the use of ABB can speed up sections of a system-on-chip when, due
to technology parameter variations, the manufactured product became too
Related links and articles:
Reality description in FP7
IMEC's Reality page
Startup offers 'variability' modeling service
CMOS statistical variability: The skeleton in the closet
IBM warns of 'design rule explosion' beyond 22-nm