LONDON – MIPS Technologies Inc., Open-Silicon Inc. and Dolphin Technology Inc. have announced the tape-out of an ASIC processor intended to operate at a clock frequency of more than 2.4-GHz when manufactured in a 40-nm manufacturing process.
The tape-out have been successful in that the design has achieved timing closure against reference flow signoff conditions from Taiwan Semiconductor Manufacturing Co. Ltd., MIPS (Milipitas, Calif.) said in a statement. The tape-out is a follow-on test chip to a 65-nm, 1.1-GHz test chip announced by Open-Silicon ( ) and MIPS Technologies at the end of 2009.
The device contains a MIPS 74Kf processor core, a superscalar, out-of-order CPU with an integrated floating-point unit, DSP extensions, 32-kbyte L1 instruction and data caches. The core is a synthesizable core with a 15-stage pipeline that is used in digital consumer devices, such as set-top boxes, and home networking solutions. As with the prior 65-nm generation design, the RTL design was done by MIPS Technologies, and implementation using memory designs from Dolphin was done by Open-Silicon. TSMC has agreed to fabricate the device using its CyberShuttle prototyping program.
Open-Silicon utilized its CoreMAX technology for design-specific library augmentation. For this design, 159 new LVt cells, 147 RVt, and 147 HVt cells were created by Open-Silicon to specifically optimize the critical paths inside the MIPS 74Kf core and FPU.
"The collaboration between Open-Silicon, MIPS Technologies and Dolphin Technology to develop one of the fastest ASIC processors ever built has proven our combined design capabilities and the strength of the model," said Naveed Sherwani, CEO and president of Open-Silicon, in a statement issued by MIPS.
Sandeep Vij, CEO and president of MIPS, said the achievement compares favorably with frequency results seen on other IP in 40-nm, and even 28-nm processes.
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