SANTA CLARA, Calif. – Adesto Technologies Corp.-a memory startup funded by Applied Materials Inc. and others-is readying its first product-a conductive-bridging RAM (CBRAM).
At the recent Non Volatile Memory Conference here, the company said it is readying a 1-megabit serial interface flash/EEPROM device. Build around a 130-nm process, the CBRAM device is based on programmable metallization cell (PMC) technology.
CBRAM is an low power, CMOS-compatible memory that is customized for a wide range of discrete and embedded markets. Adesto plans to sample what could be the world’s first CBRAM as early as the first quarter of 2011.
For some time, Adesto has been developing a so-called CBRAM, based on PMC. Some time ago, Adesto licensed the PMC technology from Axon Technologies Corp., a spinoff of Arizona State University.
CBRAM is seen as a potential candidate to replace conventional flash memory. Other candidates include FRAM, MRAM, phase-change, RRAM, among others.
''All our products are based and will be based on CBRAM memory. CBRAM can be customized to be able to replace EEPROMs, flash, etc.,’’ said Ed McKernan, senior director of business development for Adesto Technologies (Sunnyvale, Calif.).
''So to clarify, (the new device) is a CBRAM that looks and functions and is pin replaceable to current EEPROM. However with CBRAM we get a much smaller die size and therefore cost advantage over EEPROM technology,’’ he said.
Adesto’s 1-Mbit device is based on a 130-nm standard foundry process. It will integrate copper at the back-end-of-the-line process. It is said to have programmable elements that require two non-critical mask steps in the BEOL process.
The device is said to have a ''retention after cycle’’ specification of 10 years at 70 Celsius. ‘’Adesto’s CBRAM operating at just 1V eliminates the high voltage overhead of flash and EEPROM and as a result can continue to follow Moore’s Law scaling,’’ according to the company.
The 130-nm device has demonstrated the ability to have a maximum write voltage of <1.6V, a program current of <60uA, a program time of <5us per cell and an erase time of <10us per cell.
In its presentation, the company said the device makes use of a cation-based solid electrolyte technology. A key to the technology is PMC from Axon.
''The mechanism that defines memory behavior is a proprietary Axon process and uses a thin amorphous film with two metal contacts,'' according to Axom's Web site. ''It makes use of a little-known feature of some amorphous materials that can incorporate relatively large amounts of metal and behave as solid electrolytes. Under appropriate bias conditions, the metal ions in the electrolyte can be reduced to form a conducting pathway through the material but the process can easily be reversed to recreate the insulating amorphous layer.''
In 2004, Infineon Technologies AG signed a non-exclusive license for Axon's technology. The technology did not appear to fly at Infineon. Micron Technology Inc. also signed a non-exclusive license for the technology in 2001. That also did not fly.
Three-year-old Adesto took the PMC ball and has run with it. The startup is pursing a mixed product and licensing business strategy. It apparently has a foundry partner, but it declined to identify the vendor. It has several investors, including Applied, ATA Ventures, Adams Street Partners, and Harris & Harris Group.
The Text States:
"The 130-nm device has demonstrated the ability to have a maximum write voltage of less than 1.6V, a program current of less than 60uA, a program time of less than 5us per cell and an erase time of less than 10us per cell."
Well, ion conduction implies to me serious limitations in speed. I'm guessing that While in graduate school, we used millihertz frequencies to characterize ion conduction! Of course, I don't expect this to be that slow. However, milliseconds programming time is not unlikely.
I can not understand everything that is written in this article as there is a lots of prerequisite knowledge involved but i am easily impressed with the technology with keywords like low power consumption and continued scaling of Moor's law. However, in the end, it is mentioned that earlier efforts by Micron and Infineon did not fly so i wonder what would be different this time that this technology will fly.
Adesto's spec information is hard to find. CBRAM is a very interesting technology. I think it may even be a potential memristor platform. But from what I know of CBRAM, while it may use a Cu backend, the system cannot be all copper, there has to be tungsten or aluminum as well.
Samsung would be the only conceivable foundry to offer 20-30 nm half-pitch, since it is already there as a memory company. TSMC, GF, UMC are too focused on logic which is two generations behind in half-pitch.
The investigation of new memory technologies is important. But a key barrier is GB capacity is tied to 30 nm half-pitch process which is only established in dedicated memory (NAND, DRAM) lines. It would be nice if foundry could support such high densities. Otherwise these Mb-scale demos may still leave skepticism about scalability to higher densities.
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