LONDON – Research institutes CEA-Leti and Circuits Multi Projets, both based in Grenoble, France, have announced that a 20-nanometer fully-depleted silicon-on-insulator (FDSOI) process will be used on a 300-mm multiproject wafer scheduled to go in September 2011.
The MPW offer is being partly supporte by the EuroSOI+ network that collects together the main European academic partners on SOI.
FDSOI technology offers key advantages over conventional bulk CMOS technology for future nodes, according to CEA-Leti. The electrostatic integrity of the transistors is maintained because of the thinness of the body region, without the need for extra lithography steps, such as those used in the case of FinFETs, or channel doping. The consequence is a planar technology that at the same time exhibits both excellent short channel behavior and reduced variability, the research group claimed.
The basis of the manufacturing process technology is: CMOS transistors with an undoped channel and a silicon film thickness of 6nm; high-k/metal gate stack; a single threshold voltage for n- and p-type at about 0.4V; an associated design kit including SPICE model written in Verilog-A and silicon data, p-cells, DRC, LVS, schematic, parasitic and design kit documentation.
"Leti has pioneered the SOI technology for years, leading track records in the most advanced research in FDSOI, assessing its key advantages for low power, high performance applications with several industrial customers," said Laurent Malier, CEO of CEA-Leti, in a statement. "It is time now to enlarge the diffusion of the FDSOI technology enabling test cases on 20-nm process and beyond."
"CMP is very proud to offer such a very advanced process to the community. Such a process will allow researchers and engineers to experiment with the benefits of SOI on an advanced technology node," said Bernard Courtois, head of CMP, in the same statement.
Related links and articles:
CEA-Leti claims ultra-low variability in FDSOI devices at 22-nm
IMEC joins SOI Consortium
SOI's long and winding road: Are we there yet?
CEA-Leti opens 300-mm wafer line for 3-D integration