LONDON – Leading foundry chipmaker Taiwan Semiconductor Manufacturing Co. Ltd. has said it is working with a number of EDA and IP suppliers to create a 'soft' intellectual property cores collaboration program.
The intent of the program, which includes Arteris, Atrenta, Cadence, Chips & Media, Imagination Technologies, Intrinsic-ID, MIPS Technologies, Sonics, Synopsys and Vivante, is to improve soft IP readiness for advanced technology nodes.
TSMC said that under the program it is expected to provide design documents and technology information so that partners can optimize their soft IP to TSMC's manufacturing processes. TSMC did not indicate which process technologies the program is targeting.
Soft IP, which is typically synthesized from the RTL level, has for this reason been largely process technology independent with the hardening and optimization done during synthesis. Therefore the soft IP has tended not to be optimized for power, performance or area considerations. However, given the increasing complexity of the design process, collaboration is increasingly required in the creation of soft IP.
“Understanding power, performance and area trade-off inherent in large SoC designs early in the design cycle is essential,” said Dan Kochpatcharin, deputy director, IP portfolio marketing at TSMC, in a statement. "We work with soft IP partners to combine TSMC's foundry-leading technologies and manufacturing capability with their soft IP cores to address this concern."
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