PARIS – Graphics chip company Nvidia Corp. said it has licensed Mentor Graphics' Olympus SoC place and route system for its high performance graphics processors.
Nvidia said it used Olympus-SoC on multiple GPU tapeouts and outlined the overall quality of results and design schedule savings.
Mentor claimed that its Olympus-SoC place and route system addresses the performance, capacity, time-to-market, and variability challenges of advanced digital IC physical design. It concurrently optimizes IC designs for variations in lithography, process corners, and design modes to deliver the best quality of results for timing, power, signal integrity and die size.
Product features include:
• Patented MCMM optimization during all design steps
• Fast routing with full 65 nm and 45 nm rule support
• Sign-off quality timing analysis and optimization
• Extremely fast and accurate, on-the-fly parasitic extraction
• Floorplanning, rapid design feasibility and constraint debugging
• Best-in-class, CTS-aware standard cell and macro placement
• Industry’s first MCMM CTS for robust, low-power clock trees
• MCMM SI to concurrently compute delay shift and glitch for any number of mode/corner scenarios in a single pass
• Advanced physical synthesis with built-in OCV and CPPR
• Handles multi-million gate designs hierarchical or flat with faster runtimes
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.