SAN JOSE, Calif. – Cadence Design Systems, Inc. sketched out a broad strategy to provide an end-to-end flow of silicon and software design tools as part of a new EDA360 campaign. Analysts said the move is ambitious, but the company has many gaps to fill to bring the concept to reality.
At its CDN Live event here, Cadence outlined out a range of functional enhancements it will make to current and future products to provide the design tool integration it targets.
For example, Cadence said its tools will let engineers create an abstract representation for system-in-package and 3-D chip stacks to link package and chip design tools. It also promised new links between logic design, verification and manufacturing tools.
In addition, Cadence has acquired tools for virtualization and systems prototyping to expand beyond its traditional business in silicon design tools.
Once the undisputed leader in software tools for designing chips, Cadence is now vying with Mentor Graphics at second place behind archrival Synopsys that has claimed the top spot, according to EDA consultant Gary Smith.
Smith said the EDA360 vision is ambitious, but Cadence has several gaps to fill in its current silicon design flow. It has yet to deliver on its goal of creating an integrated suite of system and silicon design tools, he said.
Cadence chief executive Lip-Bu Tan said the company is focused on top technical challenges such as integrating hardware and software design and delivering low-power analog and mixed-signal design tools. The tools will help speed time-to-market, he said.
"We can no longer wait for hardware availability to start working on system design and even verification," said John Bruggeman, chief marketing officer for Cadence, a former Wind River executive.
Bruggeman said Cadence will participate in creating standards for software models that describe full systems and can be run on a virtualization platform and modified with tools Cadence will supply. The platform will use a common data model and kernel to support the very different needs of software and hardware designers, he said.
Cadence also will supply software to port those systems models to system-on-chip design tools, Bruggeman said. The software will include tools to modify and integrate silicon blocks from separate vendors into a chip design.
Finally, the SoC tools will integrate with Cadence's traditional silicon design and manufacturing tools. "We have qualified 28 nm designs with all the foundries, and have started working on 20 nm double patterning designs," said Chi-Ping Hsu who heads R&D for Cadence's silicon design tools.
The costs of designing next-generation 22 nm chips is expected to leap to $120 to $140 million, up from $50-$90 million at the 32 nm node, said Hsu. "The only ways to reduce these costs are in design automation and reuse," Hsu said.
Bruggeman said Cadence will reach out to a broad range of silicon IP, foundry and OS partners to deliver on its EDA360 vision—including the IP division of its archrival Synopsys.
Chip design costs could skyrocket to $140 million at 22nm, said Chi-Ping Hsu