PORTLAND, Ore.--IBM Research Zurich, Infineon Technologies AG and Globalfoundries Inc. have joined forces with a half dozen European universities and research centers on a mission to cut the power consumption of electronic devices by10-fold and reduce standby power to zero.
Called Steep—because of the steep cutoff slope leading to zero standby power—the European Union-funded project aims to perfect the tunneling field-effect transistor (T-FET) using nanowire channels of silicon, silicon germanium and III-V-on-silicon. The three-year $5.5 million effort aims to create processes that can be run on CMOS lines to facilitate a smooth switchover from today's complementary metal-oxide semiconductors (CMOS) to T-FETs.
"The tunneling FET [field effect transistor] has been known since 1994, but we want to give the T-FET a performance boost," said scientist Heike Riel at IBM Research Zurich. "A nanowire geometry gives optimal electrostatic performance for its gates, and the use of novel materials such as III-V-on-silicon, along with contemporary high-k dielectrics and strain engineering, will improve the tunnel FET's performance as well as significantly lower the voltage needed to operate it."
In a traditional CMOS chip, complementary p-n-p type (PNP) and n-p-n type (NPN) transistors are used. T-FETs, on the other hand, use a p-intrinsic-n (PIN) architecture, where the transistor channel is the undoped intrinsic channel between a p-doped source and the n-doped drain, controlled by a gate that enhances or shuts off tunneling across the reverse-biased channel.
To get high performance with a .5 volt power supply, IBM plans to cast the nanowire channels into III-V materials like indium-arsenide, which is not possible using traditional mask lithography, due to the lattice mismatch between III-V materials and silicon. IBM, however, has already demonstrated epitaxial growth of III-V-on-silicon with a recent tunnel diode named after its inventor, Japanese physicist Leo Esaki.
"We have recently demonstrated our III-V-on-silicon growth technique for a Esaki tunnel diode using indium-arscenide-on-silicon," said Riel.
Dr. Heike Riel, who leads the nanoscale electronics group at IBM Research Zurich, is part of Project Steep.
To fabricate the indium-arsenide on silicon, instead of using catalysts or "seeds" to initiate grow, as is often done, IBM used an oxide mask.
"We use a catalyst free method," said Riel. "We start with an oxide mask on top of the silicon that is patterned with holes and then grow with selective epitaxy the III-V material directly onto the silicon in these holes."
Those vertical columns grow a transistor channel just a few nanometers in diameter at every location on the silicon wafer where you want to build a T-FET.
IBM told me that the turn-on slope of TFETs could be as steep as 10mV per decade, compared to a 60mV per decade limit for MOS-FETs. And the negative resistance at zero volts should reduce leakage to "almost" zero.
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