Atrenta and CEA-Leti said they have defined two primary development areas.
Firstly, they will work on techniques to analyze, predict and reduce the power consumption of advanced microelectronic devices at the early stages of design, including the architectural and RTL levels.
Secondly, Atrenta and CEA-Leti said they intend to focus on the analysis and partitioning of 3D stacked die devices, also at the architectural and RTL levels. Stacked die devices are now being made possible in part by through silicon via (TSV) semiconductor process technology advances.
The joint development work will take place at the recently opened Atrenta's R&D center in Grenoble.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.