Atrenta and CEA-Leti said they have defined two primary development areas.
Firstly, they will work on techniques to analyze, predict and reduce the power consumption of advanced microelectronic devices at the early stages of design, including the architectural and RTL levels.
Secondly, Atrenta and CEA-Leti said they intend to focus on the analysis and partitioning of 3D stacked die devices, also at the architectural and RTL levels. Stacked die devices are now being made possible in part by through silicon via (TSV) semiconductor process technology advances.
The joint development work will take place at the recently opened Atrenta's R&D center in Grenoble.
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