Microchip Technology Inc. is licensing the MIPS32 M14K family of cores from MIPS Technologies Inc. to expand on its 32-bit PIC32 microcontroller family, which is currently based on the MIPS32 M4K.
The M14K cores should enable Microchip to further expand its presence in the 32-bit microcontroller market with improved performance and code density which are critical factors in embedded applications. Additionally, the M14K cores provide cost and performance scalability, while maintaining 100% code compatibility with PIC32 MCUs based on the M4K core.
A higher code density in the M14K core family was achieved through MIPS Technologies’ latest microMIPS instruction set architecture (ISA). Executing the microMIPS ISA results in at least a 30 percent code-size reduction with little or no compromise in performance. Additional features of the M14K cores that will be beneficial in the next generation of PIC32 microcontrollers include interrupt-latency improvements and low power consumption.
Sumit Mitra, vice president of Microchip’s High Performance Microcontroller Division claims the microcontroller-specific enhancements to the M14K core were heavily influenced by Microchip’s extensive experience in the embedded market and with the M4K core.
The M14K core has more than 17 licenses. The MIPS32 M14K core and M14Kc core with integrated cache-controller are the first MIPS32-compatible cores that also execute the microMIPS ISA, achieving performance of 1.5 DMIPS/MHz with an advanced level of code compression. The microMIPS ISA maintains 98 percent of MIPS32 performance while reducing code size by at least 30 percent.
The Design Article "Why MIPS is just a number" by Gaurang Kavaiya on 10/03/2010 might also be of interest. The URL is goven below:
Thank you all for keeping this discussion alive. As I am aware, the architecture of the processor matters when the processor is operated with stringent power/performance/size constraints as Smith mentioned.
@Patk0317: It will be helpful if you share your thoughts about argument presented in the article you are referring to, which says the processor architecture is not that important.
I disagree. As Sanjib mentioned below, assuming that the power and performance are similar would be incorrect. Infact, the major differentiator in many cases would be how much power a MCU would consume(making it more or less suitable for a given application) and also the performance. An architecture can result in lesser cycles/task and hence maximize the performance. Of course, you could abstract it all up to C, but when it comes to running applications under power/performance/size constraints, an architecture is all that makes a difference!
Thanks for the interesting topic you have brought up for the discussion. I agree that "assuming similar performance and power, then the selection criteria are the 3P's". But is that assumption correct? Is the performance more or less independent of the MCU architecture...even when the MCU is more than 75-80% loaded?
Assuming similar performance and power, then the selection criteria are the 3P's:
Peripherals, Pinout, Price.
As core opcodes continue to change and branch (as in this example), binary compatible operation is quietly mentioned less; The expectation is the user is insulated from that, by 'target reselect and rebuild'. aka HLL use.
Floating point may become a new differentiator, but is that a Core, or a Peripheral ?
I read an article yesterday that claims the MCU architecture is not all that important if you can code in C. The peripherals that are included on the silicon are the reason to pick a particular companies MCU. What do you think? Agree? Disagree? Why?