SAN JOSE, Calif. - For years, Intel Corp. has dismissed the need to use silicon-on-insulator (SOI) technology for its processors.
Instead, Intel has solved the power, leakage and mobility issues with high-k/metal gates, strained-silicon and other technologies. Intel’s rival, Advanced Micro Devices Inc. (AMD), has been using SOI in its microprocessors for years.
According to an analyst, Intel will reverse its strategy and embrace SOI at the 22-nm. In recent months, Intel has tipped some (but not all) details of its 22-nm process. It has certainly not talked about SOI. The chip giant tends to dismiss it.
''We believe Intel will introduce a germanium (III V) channel and full depleted SOI at 22-nm. This will give Intel a quantum leap in performance over what they are achieving and leave competitors 3-5 years behind. The 22-nm process should be in manufacturing at Intel in Q4:CY11,’’ said Gus Richard, an analyst with Piper Jaffray & Co., in a report.
''Intel's lithography roadmap is to use immersion double and multi- patterning at the 22-nm and 16-nm nodes,’’ Richard said. ''We note that Intel has consistently pushed lithography one generation further than any other manufacturer. What enables the company to do this in our view is the fact it is vertically integrated (design and manufacturing), has its own mask shop and uses restrictive design rules.’’
Then, Intel could make a switch. ''At 11-nm in 2015, Intel's options are multi-beam e-beam, EUV and quintuple patterning with 193 immersions. It is questionable whether any of these alternatives will be economically viable,’’ he said.
The chances of this happening are negligibly small... I question the analyst's conclusions. He probably just heard some rumor somewhere and is talking about it. Cost numbers for fully depleted SOI wafers are extremely high today, due to yield issues at SOITEC for thin Si layers. Intel cannot afford to manufacture with fully-depleted SOI today.
I agree that this is likely incorrect. But primarily because FD SOI combined with II-V would be a manufacturing nightmare
I have actually met with SOITEC recently, the wafer cost is significantly reduced and the cost of processed wafers is quite competitive due to a simpler process, ie, no implant to control leakage
I disagree. I think Richard is on to something. Perhaps Intel will pursue floating-body cells (FBCs) for cache designs in microprocessors. In 2008, Intel described the world's smallest FBC-based planar device on silicon-on-insulator (SOI) technology for possible use at the 15-nm node. Then, at the 2010 Symposium on VLSI Circuits in July, Intel provided an update on its ongoing research on FBCs. In a paper, Intel describes what it calls an FBC utilizing ''silicon on replacement insulator’’ (SRI) technology on a bulk substrate. Check on this: http://www.eetimes.com/electronics-news/4200210/Intel-moves-forward-with-floating-body-R-D
Hi Mark, The floating-body RAM could be more likely than doing III-Vs and Ge transistors at 22nm. However, the FB-RAM technology has some challenges... mainly dealing with signal to noise ratio, because of which its not gaining enough traction. I am hearing Innovative Silicon lost funding, and is either closing down or close to closing down. Their employees are looking for jobs throughout the Valley saying they lost funding. What do your sources tell you about the status of Innovative Silicon?
The technology matters, but what counts is what the customers say. All I can say that Intel has no major competitor if they continue to invest in cutting edge technology the way they are doing. It could turn out that before long they will acquire AMD. If Intel says they have solved a problem, believe it because they R&D is second to none.
I don't think the competeitor laws in US will ever allow the Intel acquisition of AMD. So AMD should also spend time and money in the research to compete against Intel till they stop doing anything to be in the market. Intel is able to produce the better chips because of the tight integration in the design and manufacturing. Definitely they might be working on better alternatives for the 22nm and 15nm manufactuing process.
I don't expect any major technology changes in the next 5 years, except for change from planar to something like FD-SOI and tri-gate, i.e., FinFET. However, such change is not that exciting, it's been anticipated for many years.
As discussed at BetaSights.Net (Ref: October 18th posting titled "IEDM to show 22nm alt-channels and duel- and tri-gates"), we've had all of these options available to us for many years.
What has Intel committed to for 22nm? I have no inside knowledge (unlike Mr. Richard), so I must guess based on past trends...and based on history we must guess that Intel will use alt-channels next, and that they will provide sufficient performance boost to avoid needing to use SOI for 22nm node microprocessors. However, if Intel wants to move into low-power SoC then maybe they'd need to use SOI, and maybe they can negotiate low prices from Soitec?
Strange thoughts...but as we reach the end of simple shrinks we will see more "strange" process technology strategies. However, there are many good strategic reason for Intel to never become a foundry (ignoring the strategic tie-up with Achronix), and to never buy AMD.
If I understand the LithoForum 2010 presentation correctly, even though you could have 5x patterning, you still get 6-8x density (compared to 32 nm, where they first implemented immersion), so there is still some cost benefit, though this margin is eroded.
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