Mentor Graphics Corp. is working with ARM to provide an automated memory test and repair solution for ARM embedded memories and processor cores. Interoperability has been established between Mentor Graphics Corp.’s Tessent memory test and repair solution and ARM’s family of cores and embedded memory IP.
ARM includes an optimized memory BIST bus and interface that provides external access to all memories contained within the processor core. This integrated feature enables normally intrusive memory BIST IP to be placed outside the core, removing any impact to processor performance.
Mentor's Tessent memory BIST and self-repair solution has been enhanced to fully support this interface with automatic configuration, generation and integration of memory BIST and self-repair IP that operates with an ARM processor core's specific bus and embedded memories.
The Tessent solution also supports ARM memory compiler features. ARM has developed the capability to generate a complete Tessent memory view for memory instances generated by their compilers supporting TSMC 40nm and Common Platform 32/28nm processes.
This interoperability enables a fully automated flow for adding Tessent test and repair functionality to ARM embedded memories contained anywhere within a design or processor core.
"An effective memory test and repair solution is critical to ensuring high quality levels and maximum product yield," said Simon Segars, executive vice president and general manager, ARM physical IP division. "We are pleased to be working with Mentor to ensure a robust memory test and repair solution is available to our mutual customers."
Joseph Sawicki, vice president and general manager for the Design-to-Silicon division at Mentor Graphics added, "With the huge complexity involved in testing the latest processor-based SoCs, designers need as much automation as possible to ensure that testing does not become the bottleneck in getting new designs to market."
The Tessent MemoryBIST product currently supports ARM memory compiler features. Automatic generation capability of Tessent memory views, including repair support, for ARM memory compilers for TSMC 40nm and Common Platform 32/28nm processes will be available in Q4 2010. Tessent support of the ARM Processor core memory BIST interface will be available in Q4 2010 within the standard Tessent MemoryBIST product.