KYOTO, Japan—Analog and mixed-signal chip maker Silicon Laboratories Inc. introduced a clock generator that synthesizes any eight frequencies—without the need for separate phased-locked loops (PLLs)—Tuesday (Nov. 9) at Electronica 2010 in Munich, Germany.
Silicon Labs' Multisynth technology nixes separate PLLs in favor of fractional frequency multipliers that cut power, lower jitter and shrink the size of traditional clock generators, according to company executives.
"What is really unique is that we have designed the industry's first clock generator with synthesis capabilities that does not require a phased-locked loop for each frequency, resulting in lower power, lower jitter and smaller size than traditional clock generators that require a PLL per frequency," said James Wilson, director of marketing for timing at Silicon Labs.
The Multisynth approach uses a single PLL for the whole chip, and eight separate fractional dividers that can synthesize any frequency from a single reference, which can come from an external quartz crystal, from another system clock or from an analog control voltage.
"Multisynth is our secret sauce," said Wilson. "Instead of using a different PLL for each frequency generated, what we do that is innovative is store 20-bit dividers value as a combination of an integer and a fractional multiplier, giving us enough depth to guarantee zero parts-per-million errors."
The Si5350/51 octal clock generator requires just 15 milliamps and yet claims 70 percent lower jitter and 30 percent smaller size than traditional clock generators. The Multisynth-based chips can generate eight different frequencies up to 133 MHz for applications in DVRs, HDTVs, set-top boxes, gaming consoles, printers, projectors, video conferencing systems, blade servers, single-board computers, RAID systems, femtocells and telecom equipment. For advanced application, such as temporarily over-clocking a processor, the Si5350/51 also offers glitchless frequency shifting in real time between two rates on up to six of its eight outputs.
Conventional clock generators (left) use a separate power hungry phase-locked loop (PLL) for each frequency, but Silicon Lab's Multisynth used a single PLL with fractional multipliers to cut power, cost and size.
Custom frequencies can be created by original equipment manufactures (OEMs) by loading the chips 20-bit divider registers at startup, or the factory can preprogram a set of frequencies for OEMs in just two weeks by using Silicon Labs' web-based ClockBuilder utility.