PARIS – The newly-born EDA startup Veridae Systems Inc. (Vancouver) said it has licensed Verific's front-end software, Verilog Analyzer, for integration into its Clarus family of debug and validation products.
Verific’s Verilog analyzer and static elaborator is a platform for parsing the IEEE Verilog standard. It is claimed to enable Clarus to work with a comprehensive internal representation of a RTL design rather than the original Verilog language.
Veridae said its flagship product, the Clarus Post-Silicon Validation Suite, is a silicon debug toolkit that provides visibility into the operation of complex SoCs, FPGAs and ASICs. Clarus provides simulation-style visibility into device behavior throughout the design cycle, from initial single- and multi-FPGA prototypes through IC production, according to the company. Clarus can help designers to avoid re-spins and can reduce the overall development time by 10 to 30 percent, the company claimed.
The Clarus Suite is available now. Pricing information remained undisclosed. In addition to the software suite, Veridae said it also offers on-site debug design support services.
Veridae's Clarus: Supercharged FPGA debug & post-silicon validation
In parallel, Verific said its founder and president Rob Dekker provided support regarding the technical approaches to interfacing the Verific software with the Clarus tools.
Veridae Systems was founded in 2009 with technology spun out of research activity at the University of British Columbia.