When choosing an architecture for the BRCM 5000 CPU, the design team examined several options, says Dr. Ramesh Senthinathan, a senior director of engineering in the Broadband Communication Group. "Increasing CPU performance through complex out-of-order techniques produces an exponential rise in die area and power with relatively little increase in performance," he indicated. "Multithreading turns out to be a more efficient way to achieve higher performance."
Multithreading helps fill the empty cycles caused when the CPU must access the second-level cache for data. In this case, the CPU simply executes instructions from the second thread until the first thread receives its data. Multithreading also allows the BRCM 5000 to emulate the dual-CPU structure of the predecessor BRCM 4380. Because the two threads appear to software as separate CPUs, a single BRCM 5000 core can run two operating systems.
Depending on the number of cache misses it encounters, a single-issue CPU can fill 60 to 75 percent of its execution slots on many software applications. This situation leaves relatively few slots for the second thread, limiting the performance gain of multithreading. A CPU that can issue two instructions at a time, however, will typically fill about 50 percent of its execution slots, leaving plenty of room for the second thread. According to Senthinathan, this dual-issue, dual-thread design is a "sweet spot" for multithreading, which is why Broadcom chose this approach for the BRCM 5000.
To achieve the 1.3GHz cycle time, Broadcom used a combination of custom logic and synthesized logic. For example, the clock tree is hand-designed to minimize clock skew. Critical speed paths use custom domino circuitry. Floor planning is also important, so the major circuit blocks are placed early in the process to minimize wire delays. Broadcom's Central Engineering team provided custom circuits such as high-speed SRAM and register files to achieve the high frequency.
Chips using the BRCM 5000 include a technology that Broadcom calls Adaptive Voltage Scaling (AVS). The chip contains certain test circuits that determine if it is operating near the fast-fast corner or the slow-slow corner. These test circuits contain both analog and digital functions to get a precise reading of the transistor characteristics.
For a chip with fast, leaky transistors, the supply voltage is internally lowered, reducing both leakage and transistor speed, but the fast transistors can still achieve the rated clock speed even at the lower voltage. Conversely, the voltage is increased for chips with slow transistors, boosting their performance. Thus, AVS reduces the rated worst-case power, which only occurs in fast-fast chips, while improving speed yield.
Broadcomm's reason of using MIPS is more likely a decision to maintain HW and SW re-use to the max considering one of their biggest customers is Motorola Broadband that back in the early 2000-2002 moved away from Motorola Semi 68k 32 bit cores to MIPS, ever since Broadcomm's SoC designs for the Cable boxes, modems, etc have been using MIPS driven by Motorola Broadband (formerly GI) designs.
Back in 2000-2002 ARM was making his first efforts with the ARM7 in embedded space targeting low power consumption designs, cable boxes being plugged to the wall wasn't their focuss.
At the moment ARM as grown exponentially vs MIPS because the mobile market has done the same, but we still don't see a lot or ARM away from the mobile space.
Maybe the real reason to develop your own CPU is to make it more difficult for the competition to create cheap knock-offs. To me it seem like too much of an internal cost to do this for any other reason...
This processor is the first MIPS core that challenges the ARM and Atom for performance. I think Broadcom had to do this to keep pace. The investment Broadcom has in the MIPS processor must be huge for them to invest in improving the MIPS core vs. switching to ARM.
I personally like the competition in the embedded processor marketplace. This can only benefit the consumer with more full featured products.
per core license costs are much better with MIPS. if large address space is important, MIPS had 64bit implementation in the early 90s / licenses for 64 bit for 10 years or so. there are also a ton of hw extensions for MIPS (like ARM).
Broadcom has been an old partner of MIPS so they still continue to churn out SOCs based on MIPS but with the effort they put into the power management and performance improvement I feel they could have gotten much bigger gains with ARM Cortex-A9s.
Here is a summary of some MIPS advantages according to MIPS CEO:
"MIPS has 32-bit and 64-bit processors. ARM does not have 64-bit. MIPS has single and multithreaded designs. ARM does not have multithreaded," he points out.
The only benefit of MIPS over ARM I can think of is that a lot of embedded software for things like set-top- boxes, modems and routers run on MIPS. Their licensing structure may also cost less than ARM.
Other than that, there really isn't that many technical advantages to either ISA.
IMO, PowerPC is superior to both from a design standpoint.
Broadcom has been using MIPS for processor of appliances. The industry seems to go for ARM and ARM is really taking the lead in various areas. What's the benefit of using MIPS over ARM? Is there any cost concern?
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.