PARIS – Mentor Graphics Corp. and Rohde & Schwarz said they have joined forces to deliver a hardware-accelerated debug platform for the verification of wireless communications SoCs.
The objective of this collaboration, companies said, consists in bringing complex SoC designs to market on schedule, without compromising verification accuracy or performance.
The hardware-accelerated debug platform, combining Mentor's Veloce hardware emulation technology with Rohde & Schwarz's superior test and measurement equipment, is claimed to deliver a high-performance and productive environment for handling the verification of wireless communication systems.
"By combining with Mentor and the Veloce emulator, we can show our customers a high-speed platform that allows them to perform SoC test and integration many weeks or months before they are committed to real silicon, increasing their verification productivity and improving their time-to-market," stated Gerhard Goetz, product manager, Mobile Radio Protocol Testers from Rohde & Schwarz.
Goetz added: "Our customers will be able to access a virtual hardware environment that mimics the functionality of their real silicon to debug their wireless communication chips at high-speeds using our standard test and measurement equipment and software tools."
The Veloce product family reduces project schedule and cost risk by delivering high performance simulation acceleration and pre-silicon, real world testing using SoC in-circuit emulation.
The Veloce family integrates: . Five scalable Veloce verification platforms with capacities from 8 million gates up to 512 million gates . Common configuration and debug software . Simulator-like debug environment . 100% internal DUT visibility . Network accessible, multi-user systems
The article starts off well but does not get to the good stuff, the details. How well does the virtual hardware environment emulate the real silicon (especially when it has not been implemented in real silicon)? It seems like a respin of the IKOS hardware accelerator for simulation of ASICs (running at less than full speed but much faster than software simulators). It is not very clear how this works at the nuts and bolts level. It would be a great help for wireless system development if this works! Looking forward to hearing more.