SANTA CLARA, Calif. – Seeking to lower the IC manufacturing costs for 3-D designs, double-patterning and other applications, Applied Materials Inc. has rolled out a high-throughput, ''smart'' etch system.
Competing with systems from Lam Research and others, the Centris AdvantEdge Mesa Etch tool from Applied is said to be nearly twice as fast as other etchers, thereby lowering the per-wafer cost by up to 30 percent.
The system is a new platform. It incorporates eight process chambers–six etch and two dry clean–enabling the tool to process up to 180 wafers an hour. Six chambers incorporate Applied’s previously-announced Mesa technology, which is geared for the conductor etch segment.
In comparison, Applied previous leading-edge etcher, based on the Centura platform, has four chambers, including three for etch and one for abatement. The Centura is said to process 90 wafers per hour.
In July, Applied rolled out the Mesa chamber technology for the Centura platform. Mesa is geared for both metal and silicon etch applications. That includes double-patterning, gate oxide recess, hardmask, high aspect ratio, shallow trench isolation (STI) and other applications.
Because the Centris platform has more process chambers, it will enable chip makers to reduce their production costs for both advanced memory and logic devices, said Thorsten Lill, vice president of Etch Business Group at Applied, based here.
''The new Centris platform is a game-changer for silicon etch,’’ added Ellie Yieh, vice president and general manager of Applied’s Etch Division.
In the 32-nm era and beyond, Applied, Hitachi, Lam, TEL and other etch players face more challenges than ever before: They must lower the cost of ownership in etch. ''The number of etch steps are growing,’’ as chip makers move down the process technology curve, Lill said.
This is especially true as leading-edge chip makers migrate to double-patterning as well as 3-D devices based on through silicon via (TSV) technology. Double patterning poses a huge challenge. Current 193-nm immersion lithography, based on single exposure techniques, is hitting its physical limits in terms of resolution. And the next-generation technology, extreme ultraviolet (EUV) lithography, is not ready for prime time.
So, to extend today’s optical lithography, leading-edge chip makers have or will embrace one of the many flavors of double patterning to print features on a wafer. In doubling patterning, an IC maker is essentially doubling the process steps and creating two masks, thereby boosting production costs.
In fab production, there are various methods to implement double patterning. Litho-etch-litho-etch, litho-freeze-litho-etch and spacer are among the choices. In any case, double-patterning is said to be a slow and expensive process, causing chip makers to seek new tool solutions.
In the 3-D and double-patterning era, Applied is seeking to reduce the cost of ownership in etch. In doing so, Applied has rolled out a new platform that incorporates eight process chambers, which is said to boost throughput.
In double-patterning, CD control is also critical. For CD uniformity, Applied claims its new tool can deliver from 0.5- to 1-nm, 3 sigma.
The etch chambers makes use of Applied’s previously-introduced Mesa technology. This features a new inductively-coupled plasma (ICP) source and a synchronized RF pulsing system, dubbed Pulsync.
The world’s largest fab tool maker also said it has introduced a new era of smart etching. The system makes use of self-calibration management and ''intelligent’’ software . The system software ''assures every process on every chamber precisely matches, delivering angstrom-level uniformity on every wafer,’’ according to Applied.
The tool is also said to provide a 35 percent improvement in energy savings. One system is said to save an ''Olympic-size swimming pool’’ of water per year.
@MarkLaPedus: it would be nice to know the throughput you mention (up to process up to 180 wafers an hour) is also valid for high aspect ratio TSV applications. Perhaps the eight process chambers for TSV applications might just as well make it a reality.
AS a proponent of 3D via TSV technology, I welcome this introduction to reduce cost per wafer. How ever, it would also be nice to know the limitations of the etch process using this tool for TSV's.
Dr. MP Divakar
And yet still no announcements about 450mm wafers. Not surprising how hard it is to get uniform across 300mm, let alone adding even more real estate to etch. I'm looking forward to hearing how they'll tackle 450mm.
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