PORTLAND, Ore.—Silicon chips will be communicating with pulses of light instead of electrical charge starting in 2011, according to International Business Machines Corp., which described its CMOS Integrated Silicon Nanophotonics (CISN) technology Wednesday (Dec. 1) at a tradeshow.
At Semicon Japan in Chiba, Japan, IBM (Armonk, N.Y.) heralded silicon nanophotonics as the enabler for future exascale processors that can execute a million trillion operations per second (1,000-times faster than today's petascale supercomputers).
"The CMOS silicon nanophotonics technology we have developed at IBM can meet the requirements for exascale systems, by scaling up per-chip transceiver bandwidth and integration density," said Will Green, an IBM researcher involved with the CISN project. Green worked on CISN with Yurii Vlasov, manager of silicon integrated nanophotonics at its T.J Watson Research Center in Yorktown Heights, N.Y., and fellow researchers Solomon Assefa, Alexander Rylakov, Clint Schow and Folkert Horst.
For nearly a decade, IBM, Hewlett-Packard Co., Intel Corp., Freescale Semiconductor Inc., NEC Electronics Corp., Samsung Electronics Co. Ltd., IMEC and dozens of their partners—from Avago Technologies Ltd. to Luxtera Inc.—have promised silicon photonics as the inevitable future of CMOS. By integrating electrical-to-optical and optical-to-electrical transceivers onto traditional CMOS chips, silicon photonics promises to break the bottleneck now holding back development of exascale computing platforms. IBM now claims to have solved this problem with its CISN technology which is currently being licensing to partners, and which will begin to appear in commercial transceivers starting in 2011.
"The situation is similar to when Marconi demonstrated the first transatlantic radio transmission," said Rick Doherty, principal analyst at The Envisioneering Group (Seaford, N.Y.). "Today there are oceans separating our digital systems, boards and chips, but now IBM has proven that optical interconnects can crossover those oceans using traditional, integrated CMOS lithography."
IBM's all silicon optical transceivers house modulators, wave guides, wavelength-division multiplexers, switches and detectors all cast the same CMOS die.
Since 2005, IBM Research has been assembling the silicon photonic components needed to create the entire ecosystem of CMOS optical connectivity required to enable electronic chips to communicate with light over optical interconnects instead of copper traces and busses. So far, IBM has demonstrated optical modulators, wave guides, wavelength-division multiplexers, switches and detectors—all cast in CMOS. The remaining component—a silicon emitter—was also demonstrated at IBM by adding a nanotube, but IBM's integrated silicon photonics due out next year will instead use a traditional III-V emitter.
One major stumbling block recently removed by IBM for its CISN technology was the ability to bury a germanium layer at the bottom of its CMOS stack. Others like Freescale, working with startup Luxtera, have demonstrated silicon optical transceivers using that use a germanium-last process, but IBM claims its germanium-first process enables a 10-to-1 reduction in die size, enabling 65-nanometer CMOS chips to house silicon optical transceivers in just a half a square millimeter (which can be ganged together for terabit-per-second speeds in less than five-by-five millimeters).
IBM is currently characterizing the manufacturability of its CISN process in commercial foundries, and predicts that the first availability of CMOS optical transceivers from its licensees will begin next year. IBM predicts that its CISN will then work its way from connecting systems to connecting boards in the same system, to connecting chips on the same board, to eventually connecting cores on the same CMOS microprocessor by 2016.
For a direct bandgap material, like III-V, an electron near the bottom of the conduction band can recombine with a hole is near the top of the valence band, annihilating the electron and releasing its energy as a photon. Unfortunately, in an indirect band gap material such a process would violate the conservation of crystal momentum.
That, of course, is one of the issues that IBM engineers are working on as we speak. And you can bet IBM is also working on process/material/archtectural innovations to overcome the hurdles to silicon emitters.
Yes, Intel has successfully grafted a flake of III-V onto a silicon chip as an emitter, but not in a production environment. I believe that instead of fabricating III-V materials on CMOS chips, that instead IBM is figuring on using a traditional discrete III-V emitter and just piping its emissions onto its CISN chips with fiber optics, where the silicon modulators will take over translating electrical data into optical data.
Good emitters need to have a direct bandgap so that electrons in the conduction band can annihilate a hole in the valence band, thereby releasing the excess energy as a photon. Silicon has an indirect bandgap that prevents it from being a good emitter.
I thought of this idea of using air-gaps as waveguides when I was interviewing IBM, but then forgot to ask about it. My best guess is that the people working on air-gaps are not in the same huddle as the guys working on silicon photonics. Maybe when both technologies are a little more mature, there will be some cross-fertilization.
Intel has many of the components for silicon photonics, including a hybrid emitter that uses a III-V flake, but IBM claims it is the only vendor that has downsized its photonic components enough to make them commercially feasible.
Thank you Colin. Yes, silicon emitter would have poor performance, carbon nanotube based or else (BTW, carbon nanotube laser sounds like a long shot)...and III-V laser would be lower cost, but only if manufactured in III-V process...I think it will be very expensive if manufactured in silicon process, imagine how many process steps will be require to add that laser, enormous complexity, hardly a manufacturable solution! Kris
IBM has a silicon emitter, but it is a hybrid that uses a carbon nanotube: htp://bit.ly/eHrLjj
However when I asked IBM about it, they said cost-wise no silicon emitter could yet compete with III-V emitters in performance or cost, and until they do no one should switch.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.