LONDON Samsung Electronics Co. Ltd. has announced an 8-Gbyte (64-Gbit) registered dual-inline memory module (RDIMM) with through-silicon-via (TSV) die-stacking that it claims saves 40 percent of the power consumption of a conventional RDIMM.
The memory module is based on multiple DDR3 DRAM die made using a 4X-nm process technology. It has been tested by Samsung customers and delivers superior performance because of its use of three-dimensional (3-D) chip stacking using TSVs, Samsung said.
We plan to provide TSV-based devices in line with the expected introduction of TSV-enabling chipsets, which are now slated to arrive in the second half of 2011, according to a spokesman for Samsung.
TSV technology creates micron-sized holes through the silicon die and
fills them with copper. By using a TSV bonding process, instead of
conventional wire bonding silicon wires are shortened. The technology is
the key to solving the paradox of lowering absolute power consumption
while increasing memory capacity and system performance, Samsung said.
The reduced energy consumption allows modules to be brought closer together without overheating problems therefore allowing for an improvement in system-level memory density, Samsung said. This is expected to be important in next-generation servers where there is predicted to be a 30 percent drop in memory slots, Samsung said. The use of TSVs will enable DRAM density to rise by more than 50 percent to offset this and making it a suitable memory option for high-performance servers, the company added.
Widespread adoption of 3-D TSV technology is expected to take place from 2012 and Samsung plans to deploy TSV technology in 3X-nm and finer process nodes, the company said.
Met with Samsung personnel this past week. This is the frst of their 3D TSV products to be introduced. It us a simple 2 chip connection (i.e. 2 4Gb DRAMs). Connections are done in copper. Report is they will not persue tungsten for mechanical and electrical reasons. See more and keep abreast of all things 3DIC at "Insights From the Leadng Edge"...
@newcoding: If we assume that half of the power is dissipated in active cells and half in interconnects to achieve 40% reduction in total power dissipation one would have to shrink interconnect portion by an order of magnitude, sounds too good to be true...Kris
This was predicted and to be expected if one followed the Elpida/UMC announcement months ago. Samsung response was overdue. Samsung has been working on this technology for more than 5 yrs.
Follow all 3DIC tecnology advancements on IFTLE (Insights from the leading edge) at Solid State Technology web page....
Well its a great news for electronics industry if Samsung has come up with DRAMs that cuts power consumption by 40% looking at memory being the most important part of the design. They seems to be pretty confident on TSV technology. When the industry start using it the pros and cons would come out. But for now it really brings advantages on the table.
@Peter Clarke: thanks for the expose on this. At the last Global Foundries Technology Conference at Santa Clara, one of the Samsung spokesperson was apparently alluding to the product announcement we know now as the 8Gb RDIMM. It looks like this is one of the first products to go into production using the TSV technology.
Given the multitude of problems one can encounter in 3D stacks (like mechanical stability, CTE mismatch between Cu and Si, thermal management, 3D routing & floor planning, etc) I would be curious to know what the yields are and the number of dice in the stack. Better yet, I would love to get my hands on one of these RDIMMS and do a teardown!
Dr. MP Divakar
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