SAN FRANCISCO ĖDuring the International Electron Device Meeting (IEDM) here, Japan's Renesas Electronics Corp. is moving to propel its embedded DRAM efforts into the 28-nm era and beyond.
Renesas has devised a cylinder-type, metal-insulator-metal (MIM) capacitor in a porous low-k film (CAPL) for embedded DRAMs. Dubbed Logic IP Compatible (LIC), the technology from Renesas is compatible with standard logic CMOS and uses a porous low-k film with a k-effective rating of 2.5.
The technology enables a pore size of about 0.4-nm at 28-nm, compared to a conventional pore size larger than 1-nm. For the 40-nm node, the low-k film is not porous but is rigid. LIC can be used at the 28-nm node and beyond, said Hirohito Watanabe, general manager of the LSI Research Laboratory at Renesas (Tokyo).
Today's embedded DRAMs are based on a conventional capacitor over bit-line technology in a silicon dioxide pre-metal-dielectric. The conventional structure is a straightforward solution to insert add-on process for MIM capacitors into the CMOS technology.
But scaling the CMOS technology from 40- to 28-nm could "bring significant increases in parasitic resistance and capacitance" in embedded DRAM structures, according to Renesas.
Renesas proposes a new CAPL structure, in which the MIM capacitor is integrated into the porous low-k film in the copper-metallization layer, said Yoshihiro Hayashi, senior chief engineer in the LSI Research Laboratory at Renesas.
"Cylinder MIM capacitors are embedded into interconnect layers to eliminate long bypass contacts with large RC delay," Hayashi said.
"In order to suppress the metal contamination in the porous film, the MPS (molecular pore stack) with closed pore structure is preferable for this type of application," according to a paper on the topic that Renesas representatives are scheduled to give Wednesday (Dec. 8) at IEDM.
"It is found that the gas-phase diffusion through the pores in the low-k film is possible during CVD process of the MIM electrodes. Small-closed pore is essential to eliminate the metal contamination in the CAPL structure," according to the paper.
"The MPS SiOCH film (k=2.5) with very small pores less than 0.5 nm completely blocks the gas-phase diffusion of metal precursors especially for CVD-TiN. The CAPL with the MPS SiOCH film was successfully fabricated into a BEOL structure compliant to a 28 nm-node without degradation of dielectric reliability. The CAPL structure is extendable to keep scaling of eDRAM devices beyond 28 nm-technology," according to the Renesas paper.