BURLINGAME, Calif. – 3-D chips based on through-silicon vias (TSVs) are moving past the ''PowerPoint engineering’’ stage, but issues remain with the technology, according to an analyst.
TSV-based 3-D devices have been in the works for years. But except for select products, the technology has not moved into the mainstream, limiting TSV to R&D or mere ''PowerPoint slides.''
''3-D TSV looks easy in (a) PowerPoint,’’ said E. Jan Vardaman, president of TechSearch International Inc., a research firm, at the 3-D Architectures for Semiconductor Integration and Packaging event here. ''PowerPoint engineering has high yield. 3-D TSV production today does not.’’
In a presentation, Vardaman said TSV-based 3-D has moved into the engineering stage, but mass production remains a moving target. Initially, chip makers could move towards a so-called 2.5-D device based on an interposer technology, which could hit the mainstream in 2012 or so. A full-blown TSV-based 3-D chip may not hit the mainstream until 2013 to 2015, according to analysts.
Experts define a true 3-D package as one that stacks various chips vertically and then connects them by deploying through-silicon vias (TSVs). The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths.
So far, chip makers are shipping limited 3-D devices based on TSVs, mainly CMOS image sensors, MEMS, and, to some degree, power amplifiers.
There are several problems with TSV technology: Lack of EDA design tools; complexity of designs; integration of assembly and test; cost; and lack of standards.
''3-D TSV technology has moved past ‘PowerPoint’ engineering into real engineering work,’’ she said. ''Structures have been fabricated.’’
One of the big announcements in the arena was Xilinx Inc., which recently discussed a ''stacked silicon interconnect’’ FPGA. The Xilinx announcement is key ''in the establishment of a TSV infrastructure,’’ she said. ''Infrastructure is the key in the adoption of new technology.’’
In the presentation, she listed the issues that must be resolved in the TSV arena:
1. Design guideline and software must be available
''Current design tools (are) not easily extended to 3-D ICs,’’ she said.
2. Thermal solutions must be developed especially for memory and processor.
3. Foundries must have design rules and qualified production lines
''Foundries (are) installing 300-mm mass production lines, but many (are) not ready for high-volume until 2012 and some even later,’’ she said.
4. The use of silicon interposer and other alternatives could delay TSV adoption
5. Who will provide the bump, assembly and test?