BURLINGAME, Calif. – 3-D chips based on through-silicon vias (TSVs) are moving past the ''PowerPoint engineering’’ stage, but issues remain with the technology, according to an analyst.
TSV-based 3-D devices have been in the works for years. But except for select products, the technology has not moved into the mainstream, limiting TSV to R&D or mere ''PowerPoint slides.''
''3-D TSV looks easy in (a) PowerPoint,’’ said E. Jan Vardaman, president of TechSearch International Inc., a research firm, at the 3-D Architectures for Semiconductor Integration and Packaging event here. ''PowerPoint engineering has high yield. 3-D TSV production today does not.’’
In a presentation, Vardaman said TSV-based 3-D has moved into the engineering stage, but mass production remains a moving target. Initially, chip makers could move towards a so-called 2.5-D device based on an interposer technology, which could hit the mainstream in 2012 or so. A full-blown TSV-based 3-D chip may not hit the mainstream until 2013 to 2015, according to analysts.
Experts define a true 3-D package as one that stacks various chips vertically and then connects them by deploying through-silicon vias (TSVs). The aim is to shorten the interconnections between the chips, reduce die sizes and boost device bandwidths.
So far, chip makers are shipping limited 3-D devices based on TSVs, mainly CMOS image sensors, MEMS, and, to some degree, power amplifiers.
There are several problems with TSV technology: Lack of EDA design tools; complexity of designs; integration of assembly and test; cost; and lack of standards.
''3-D TSV technology has moved past ‘PowerPoint’ engineering into real engineering work,’’ she said. ''Structures have been fabricated.’’
One of the big announcements in the arena was Xilinx Inc., which recently discussed a ''stacked silicon interconnect’’ FPGA. The Xilinx announcement is key ''in the establishment of a TSV infrastructure,’’ she said. ''Infrastructure is the key in the adoption of new technology.’’
In the presentation, she listed the issues that must be resolved in the TSV arena:
1. Design guideline and software must be available
''Current design tools (are) not easily extended to 3-D ICs,’’ she said.
2. Thermal solutions must be developed especially for memory and processor.
3. Foundries must have design rules and qualified production lines
''Foundries (are) installing 300-mm mass production lines, but many (are) not ready for high-volume until 2012 and some even later,’’ she said.
4. The use of silicon interposer and other alternatives could delay TSV adoption
This "PowerPoint" analysis is great. I think it's better than my Dew Point analogy that I have been working with at my blog. Dylan's point is so true. I think I have been through that Monday morning slide deck myself. So many things seem to begin and end in the Microsoft software. Whether it's collecting thoughts, planning a strategy or actually communicating the message in the end, it's often "Death by PowerPoint." Engineers and others who tire of this, but may need to use the software and the medium for real purposes should check out an excellent presentation by that title on SlideShare. Just Google that title.
Hey, it isn't going to get anyone over the vaporware hump, but better presentations might reduce the market for anti-depressants. And that makes me wonder if anyone has compared the related effectiveness or cost-benefit comparison of water-boarding versus PowerPoint.
A similar joke is to tell a customer we will put our best Powerpoint engineer on the job.
That aside, regardless of the interconnect between the layers, each layer will generate some heat. The TSV's and the programmable anti-fuses of NuPGA
will have to conduct the heat to the base wafer, and also the top wafer (assuming a heatsink contact there). Otherwise, one is restricted to very low power devices.
While there is clearly products that can benefit from the approach, the holy grail would be to put any function block anywhere necessary in a 3-D structure, truly building a system in a block. Nothing says the individual wafers have to be the same process so long as the inter-connects do their signal and heat transfer functions.
Oh...and those darn I/O leads. Yeah...we gotta get them to the outside world too.
Frank, I like that one. Good joke.
I would also point out that we all know some people who are so accustomed to using Powerpoint as a crutch and talking through slides that I bet if you asked them about their weekend they'd just as soon answer by walking you through a deck.
It's great to see that 3D TSV is making progress, despite the fact that "Powerpoint engineering" is rampant in many realms of our industry -- not only 3D TSVs. Just ask any marketer what the customer wants for his next SoC, and you can have beautiful Powerpoint slides within a week, showing the finished product as he or she envisions it, as if it were already in mass production.
Back when I used to spend some effort on system to silicon design methodologies, we used to joke about the next phase being Powerpoint-to-silicon design methodologies.
It's still a joke, but still there are some people who don't get that.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.