PORTLAND, Ore.—True monolithic three-dimensional (3-D) silicon chips will beat die stacked with through-silicon-vias (TSVs) by a factor of 10,000 in connectivity, according to serial entrepreneur Zvi Or-Bach, founder of NuFGA Inc. and a past winner of the EE Times Innovator of the Year Award. Or-Bach will show how to make true monolithic 3-D chips at the 3-D Architectures for Semiconductor Integration and Packaging conference in Burlingame, Calif.
"We have been able to make significant progress in monolithic 3-D, and now have the intellectual property (IP) in place for two methods," said Or-Bach, who pioneered ASICs at eASIC and later at Chip Express and is now president and CEO of startup NuPGA (San Jose, Calif.).
According to Or-Bach, NuPGA's 3-D IC fabrication techniques can be used to stack memory on top of a processor, to stack bit-wide memory chips into byte-wide configurations or just to shrink the die of existing designs by optimizing chip area versus height. Any number of chip layers can be composed, according to Or-Bach, enabling general-purpose monolithic 3-D to reduce chip areas by as much as three times over conventional 2-D.
"Others like BeSang have found ways to put vertical transistors on top of logic, for instance as memory cells, but we have discovered a two ways to make horizontal transistors, which can be used for almost anything," said Or-Bach.
The simplest way to create 3-D chips is to fabricate
the bottom chip as usual, cover it with oxide, then bond it to a
similarly oxide clad giant-transistor donar chip, which can then be
etched into individual transistors.
The main problem with going 3-D is that the temperatures required to create conventional silicon transistors on the top layer—up to 900 degrees Celsius—will melt the already formed transistors on the lower layers. NuPGA's technique sidesteps that issue by bonding a top wafer that has already had its high-temperature processing done, leaving only low-temperature etching and metallization to finish the 3-D design.
Both techniques start with a finished CMOS chip for the bottom layer, which is then covered with an insulating oxide and bonded to the donar wafer. In the first technique, a donar wafer is fabricated into a single giant transistor. After bonding, the giant transistor can be etched into individual transistors which are then interconnected with metallization.
To create 3-D chip layers with both n-type and p-type transistors, the donar chip must already be fabricated with dummy gates, which can be etched and interconnected after wafer bonding.
NuPGA's second technique fabricates a sea of transistors on the donar wafer, but each with a dummy placeholder for its gates. After a novel bonding step, which aligns the chips with an effective accuracy of 100 nanometers, the top layer transistors are finished by etching out the dummy gates and adding the top metallization layer.
NuPGA hopes to license its techniques, which have yet to be proven out with 3-D prototype chips, to existing semiconductor makers.