SAN FRANCISCO – At the International Electron Device Meeting (IEDM) here this week, there were three apparent themes.
First, the number of relevant technical papers was down this year. Second, there is still a lack of consensus about the next-generation transistor structure for the future nodes. And despite a flurry of new and exotic technologies on the horizon, chip makers still insist that economics and cost will drive their future transistor and process decisions.
In the past, a number of chip makers were chasing after Moore’s Law and developing leading-edge processes, which led to a plethora of relevant papers at IEDM. Today, there are fewer leading-edge chip makers, contributing to a ''big drop’’ in papers at this year’s event, said Meikei Ieong of Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) and general chairman at IEDM. ''I don’t see (the amount of IEDM papers from the peak years) coming back,’’ he said during an event.
There could be other reasons for a decline in papers. In the past IEDM events, leading-edge chip makers were more open and would often provide a hint on what’s coming on the horizon. IBM, Intel, Samsung, Toshiba, TSMC, UMC and others would reveal their latest and greatest processes amid an avalanche of papers.
At this years’ event, there were few papers that provided clues on what vendors would do next. Many leading-edge chip makers kept their cards close to the vest and didn’t want to reveal their directions to their rivals. Many of the papers were more academic in nature or were short on detail, leaving some attendees disgruntled.
At IEDM, however, there were many rumors flying on what leading-edge, digital chip makers may use for the transistor structure at 22-/20-nm. Most believe the leading-edge foundries will extend bulk CMOS.
There is much speculation what Intel Corp. will do at that node. Some believe Intel will extend bulk CMOS. Others think the chip giant could go to fully-depleted-or sometimes called extra thin silicon-on-insulator (SOI). One source even thinks Intel is looking at tri-gate structures at 22- or at 15-nm.
The wild card among the technology candidates is 3-D based on through-silicon vias (TSVs), which is not process dependent. If chip makers can produce TSV-based 3-D chips in volumes-and at reasonable costs-it could throw a wrench in the entire roadmap.
At present, leading-edge chip makers are using conventional bulk CMOS and planar transistor structures for the 32-/28-nm nodes. But clearly, there is still ''angst over the 20-nm node and what transistor would be picked,’’ said G. Dan Hutcheson, CEO of VLSI Research Inc. ''As for transistor structure, the safe bet is that we will extend conventional CMOS another generation.’’
Joanne Itow, an analyst with Semico Research Corp., agreed-and for good reason: Cost. It is simply too expensive and risky to move new and exotic transistor structure at 22-/20-nm, Itow said.
Just how long chip makers will be able to extend today’s bulk CMOS remains murky. After 22-/20-nm, there is little agreement among chip makers about the de facto transistor structure for the 16-nm logic node, which is expected to appear in 2013 or so. There are a number of candidates on the table: III-V, bulk CMOS, FinFET, fully-depleted silicon-on-insulator (SOI), multi-gate, among others.
And in the distant future beyond 16-nm, the field is wide open between current technologies as well as a range of exotic structures, such as III-V, carbon nanotubes, graphene, quantum well FETs, among others.
''22-nm will likely be planar,'' said Dean Freeman, an analyst with Gartner Inc. ''Intel could surprise us with a trigate. We will know when they release the SRAM announcement in the next six months. SOI is unlikely for Intel at 22-/20-nm.
''What is likely at 22-/20-nm is additional channel engineering to improve mobility. Strain, possibly geramium in the channel, maybe some SiC or SiP for the N channel devices,'' Freeman said. ''At 15-nm, I would expect a mulitgate transistor (FinFETs or trigate depending upon who you are). SOI is a possibility. If you go to a trigate, there is less contact with the substrate, thus less leakage, and thus less need for SOI. I would expect trigate for at least two generations. Past 12-nm, it depends upon a lot of things. If graphene is far enough along, it would be a likely candidate, but there are many hurdles to overcome. The III V gate is a possibility, however, you might see this more for niche applications as it will be expensive. Multigate with new materials is another possibility, I think nanotubes as the gate are unlikely, unless someone develops a killer manufacturing process.''
Still others had another opinion. ''My guess (is that the transistor) would be still planar at 20-nm,'' said Dick James, an analyst with Chipworks. ''The industry may also split. Some will do FinFET. Some planar. (I see) no fancy III V materials at this node. (At 15-nm) I could see the full move to FinFET and/or ultra-thin SOI, and possibly the III-Vs moving in-certainly by 11-nm.''