BANGALORE, India—System design will pose the main challenge to the EDA industry as a whole in the decade starting 2011, according to Mentor Graphics Corp. Chairman and CEO Walden Rhines, who added that his firm is amongst the better prepared EDA vendors to address this.
Speaking at the annual Mentor international users meet here, Rhines said the 2000-2010 decade saw the largest growth areas being in design for manufacturing (DFM) and electronic system level (ESL) segments.
"These two major methodology changes meant that EDA moved from the bounds of just designing a chip to supporting the manufacturing of a chip with manufacturing technology and that opened up new revenue," Rhines said. "ESL moved us from the traditional Register Transfer Language (RTL) design up one level and this too opened up new revenue opportunities."
According to Rhines, EDA revenue—which has stagnated at between $4 billion and $5 billion for the past several years—can grow as new problems arise and new methodologies take off.
"Yes, I do see total EDA revenues increasing," Rhines said. "It is just that it will not come from people buying more simulators. It will come from other major changes, the whole paradigm change with more and more design is done at higher levels of abstraction, C-based design, synthesis, and where there is more hardware and software co-verification is done both in software at the transaction level and done with emulators at the hardware level."
While there was a slight decline in the number of venture-funded EDA startups during 2000-2010, the number of new companies remained relatively stable, according to Rhines. There were many more startups in the earlier part of the decade, including roughly 20 in DFM at one time, but they all got acquired or folded, Rhines said.
The next decade is going to be one of system design challenges, requiring disparate technologies to be brought together, Rhines added. Mentor is better prepared in system-level design because of its acquisition direction of resources in this area, Rhines said.
Specifically, design for low power will be among the challenges, Rhines said, advocating a holistic approach. Optimizing for performance and power needs to be addressed by ESL-based design, he said.
The explosion of complexity in functional verification is another challenge, which can be met by maximizing verification per cycle, Rhines said. While place-and-route timing and power closure can be addressed by multi-corner, multi-mode (MCMM) capabilities, the rising complexity in physical verification needs to be addressed to accelerate manufacturing closure, Rhines said.