SANTA CLARA, Calif. - In a stunning development, IBM Corp.'s ''fab club'' is switching high-k camps.
After pushing the gate-first high-k approach for the 32- and 28-nm nodes, IBM's technology partners will move to rival gate-last technology at the 20-nm node. IBM's partners include AMD, Globalfoundries, Samsung and others, all of which insisted that the gate-first approach was better-until now.
For 20-nm, ''gate-last is a better approach,'' said Gary Patton, vice president of the Semiconductor Research and Development Center at IBM Corp., at the Common Platform technology event here. Compared to gate-first high-k technology, gate-last will provide some density and scaling advantages at 20-nm, he said.
In other words, IBM and its partners have acknowledged that its highly-touted, gate-first technology is basically a one-node solution. Intel, TSMC and UMC are proponents of gate-last technology. Intel has been in high-k production since the 45-nm node. TSMC is expected to ramp high-k at 28-nm.
For some time, one of the partners in IBM's alliance-Samsung Electronics Co. Ltd.-has dropped hints it would prefer the gate-last approach. At the recent 2010 IEEE International Electron Devices Meeting in San Francisco, Samsung presented a paper on a rival technology: ''gate-last high-k/metal gate devices.''
Initially, Samsung plans to roll out a gate-first, high-k technology. As previously reported, the technology will be offered at the 32- and 28-nm nodes for foundry customers. GlobalFoundries will also ramp up the technology based on gate-first.
But even Samsung reportedly sees gate-first as a one-node solution and is pushing the gate-last technology. This in turn may have tipped the scale within IBM-a blow for Big Blue. IBM has been researching gate-first for about a decade and claimed this was the best approach. Several years ago, IBM also switched low-k camps, when it dropped the spin-on glass approach in favor of chemical-vapor deposition, it was noted.
Except for Intel, leading-edge chip makers are struggling to switch from today's silicon dioxide to a high-k gate insulator. Silicon dioxide as a gate dielectric is running out of gas at 45-nm, but some are pushing it to 28-nm.
But high-k has been delayed because of difficulties in developing the technology. In addition to high-k, chip makers must also move to metal gates, replacing the N and P doped polysilicon gate electrodes with metallic alloys to eliminate polysilicon depletion at the gate.
There are two basic approaches to the next-generation gate stack in logic designs. IBM's ''fab club'' is using a gate-first approach, while Intel is deploying a rival replacement-gate or gate-last technology. In a gate-first approach, the gate stack is formed before the source and drain, as in a conventional CMOS process. Replacement-gate technologies are a gate-last approach, where the gate stack is formed after source and drain.
In an interview with EE Times, Patton said IBM's techology alliance made the ''right decision'' to go with gate-first at the 32- and 28-nm nodes, because it provides a 10 percent to 20 percent performance advantage over gate-last.
He dismissed the notion that IBM and its partners are struggling with its gate-first technology, prompting the shift to gate-last. ''32-nm (based on gate-first, high-k) is done and qualified,'' he said. ''The challenges are behind us.''
For its part, Samsung is ramping up 32-nm gate-first, high-k, with 28-nm on the horizon.
At 20-nm, however, IBM's "fab club" believes gate-last provides better "price-performance," Patton said.
IBM is no stranger to gate-last. IBM has deployed a gate-last technique when using silicon dioxide gate stacks during the past nodes. IBM has also been working on gate-last high-k in parallel with gate-first. So moving to gate-last high-k was a simple extention, he said.