SAN FRANCISCO—Altera Corp. Monday (Jan. 24) divulged details of its 28-nm FPGA product portfolio, which company executives said they believe will be the broadest and most diverse of any FPGA supplier.
Altera (San Jose, Calif.), which previously announced that its 28-nm Stratix V devices would begin sampling late in the first quarter, said Monday that 28-nm Arria V and Cyclone V FPGAs would begin sampling late this year and early next year, respectively.
With its 28-nm products, Altera is emphasizing different offerings specifically created to address the diverse design challenges of each of its customers. According to Luanne Schirrmeister, Altera's senior director of component product marketing, 10 years ago a single FPGA could adequately meet the needs of most applications that were using programmable logic. But today, Schirrmeister, the requirements for various applications using FPGAs are much more diverse, requiring greater speed at the high end and lower power consumption at the midrange and low end.
"We strongly believe that one size does not fit all," Schirrmeister said. "We think that our products will have a better fit to the customers' applications because of the unique things we are doing for each of those markets."
Altera has previously said that it would use Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC)'s high-performance manufacturing process for its Stratix V parts and TSMC's low-power process for its Cyclone V and Arria V devices.
Altera's 28-nm devices will include hard system-level IP to help customers meet cost, power and performance requirements. Examples include PCI Express (PCIe) Gen2 x1 and x4, PCIe Gen3 x8, Interlaken, 40G/100G and 100 Gigabit Ethernet (100GbE).
Schirrmeister said that for high-end Stratix V devices, Altera has effectively hardened 530,000 logic elements. "We want to win on the unique differentiation of the IP we can supply in key markets," Schirrmeister said.
But for users of midrange Arria and low-end Cyclone products—a significantly larger customer base—hardening too much IP would decrease flexibility and penalize customers who couldn't use the various hardened blocks. "It’s quite an art to get that just right," Schirrmeister said. "I’m confident that these choices will be good choices."
Arria V and Cyclone V devices will also include hard memory controllers supporting several standards. “I think they are going to be extremely popular," Schirrmeister said.
But she added that Altera pitched the idea of adding hard memory controllers to Stratix V and customers rejected it. Stratix V devices will utilize soft memory controllers.
According to Altera, the Cyclone V family offers 40 percent lower total power versus the previous generation 60-nm Cyclone IV. Cyclone V FPGAs will also feature 12 transceivers operating at up to 5 Gbps, hardened PCIe Gen2 x1 blocks, and hard memory controllers supporting LPDDR2, mobile DDR and DDR3 external memory.
Arria V devices will also offer 40 percent lower total power versus previous generation devices, Altera said. The Arria V family devices include transceivers operating at up to 10 Gbps, hard memory controllers supporting DDR3 external memory, and efficient systolic finite impulse response (FIR) filters with variable-precision DSP blocks, according to the company.
Altera said the maximum transceiver data rates in Stratix V GX FPGAs were increased to 14.1 Gbps to support emerging high-speed protocols, including FiberChannel 1600. The density of Stratix V GX was also increased to 1.1 million logic elements in a monolithic die, the company said.
Altera said its HardCopy V ASICs will deliver higher performance for transceivers, I/Os, and core logic; with higher levels of logic and memory integration compared with previous generation offerings. HardCopy V ASICs now support a wider range of high-volume applications which require low power, lower unit cost, or improved single-event upset tolerance in production, the company said.
Altera's 28-nm device portfolio will be supported by its Quartus II development software, Altera said. Quartus II includes a new Qsys system-level integration tool that simplifies IP integration and offers access to a embedded processor options, including a hardened ARM Cortex-A9 MPCore, the company said.
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