The folks at Xilinx just announced their participation at DesignCon 2011 in Santa Clara, California from January 31 through February 3, 2011. Throughout the week, Xilinx experts will share their insight about overcoming design challenges, improving signal integrity problems, understanding Through Silicon Via (TSV) processes, and meeting chip to chip I/O demands. Xilinx will also be exhibiting demos with MoSys, SiSoft, and Agilent, all featuring Xilinx's Virtex-6 HXT FPGA. Xilinx Senior Vice President and Chief of Technology Officer, Ivo Bolsens, will keynote on how the industry is entering an era of crossover SoCs.
Keynote Wednesday, February 2
12:00 - 12:30 pm, ChipHead Theater Entering the Era of Crossover SoCs, by Xilinx Sr. Vice President & CTO Ivo Bolsens
Global consumer markets continue to drive the need for ubiquitous computing and an insatiable thirst for communications bandwidth, which are fueling the growth of the electronics industry. Yet the cost of building custom SoCs to support many of the emerging applications is becoming increasingly difficult to justify - except for the highest volume devices. Rising to this challenge, a new class of "crossover SoCs" is emerging that combines many of the strengths of custom SoCs and FPGAs in a single device. In this session we will discuss the different approaches underway in the industry, including embedded processing subsystems, 3D interconnect technology, SiP and others, and how they will reshape the device landscape over the next decade.
Panel Discussions Tuesday, February 1
3:45 – 5:00 pm, Ballroom F FPGA Caveman meets FPGA Chiphead FPGA Design Tools and Methodologies: Can they keep pace?
Xilinx Sr. Vice President, Worldwide Marketing,Vin Ratford will join the panel in discussing the
performance and capabilities of 28nm FPGA devices and how FPGA vendors are providing ways for end users to integrate IP into FPGA architectures. This panel will examine the key pain points in the FPGA design process, look at unique design needs, and discuss new design tools, methodologies as well as the greater opportunity for a true commercial FPGA EDA tool industry.
3:45 – 5:00 pm, Ballroom G How to Avoid Butchering S Parameters Xilinx Senior Staff Design Engineer, Mike Jenkins will join the panel in discussing ways to avoid producing bad quality S parameter files for high speed serial channels. Specific topics will include causality, passivity, reciprocity, de-embedding, reference planes, and measurement techniques. Through a discussion of the advantages and disadvantages of each point of view, attendees will gain a broader understanding of S parameters in general and what it takes to produce good S parameter files.
Wednesday, February 2
2:00 – 2:50 pm, ChipHead Theater Back to Edison, Back to Innovation Xilinx Sr. Vice President & CTO Ivo Bolsens will join an esteemed panel moderated by BDTI
President Jeff Bier and including National Instruments President and CEO Dr. James Truchard and University of California EECS Professor Edward Lee. Inspired by the June 5, 2010 issue of TIME magazine, which recounted the impact of Thomas Edison's idea factory and his relevance today, the panel will provide a modern look at Edison's approach to ideas and results - "a minor invention every 10 days and a big thing every six months or so" - taken from the January 3, 1888 page in Edison's idea book.
3:30 – 4:30 pm, Room #208 Meeting chip to chip I/O demands of 100G & beyond line cards
Xilinx System Architect Communication Platform Definitions, Manoj Roge will join the panel in
discussing trends and alternative solutions for interconnecting chips on 100 Gbps & beyond line
cards that maximize throughput while minimizing pin count, die area and power.
3:45 – 5:00 pm, Ballroom G Designing FPGA-based PCBs
Xilinx Senior Director of Systems & Applications Engineering, Andy DeBaets will join the panel in discussing the problems of designing FPGA based PCBs. This panel will address the designer challenges of optimizing the FPGA design across multiple domains, schematics and FPGA timing and explore ways to solve them.
Wednesday, February 2
9:20 – 10:00 am, Ballroom K Through Silicon Via Design Considering Technology Challenges
Xilinx Staff Signal Integrity Engineer, Namhoon Kim will deliver a paper on a new approach for
successful implementation of TSV for multi-gigabit or tens-of-gigabit per second SerDes application, possible mechanical and reliability issues on TSV process, and will also cover technology requirements and common challenges.
Tuesday-Wednesday, February 1-2 MoSys and Xilinx Virtex-6 HXT FPGA demo at Booth #516
As a new GigaChip Alliance participant, Xilinx will be showcasing a Virtex-6 HXT FPGA, the
industry's highest bandwidth FPGA, interoperating with the MoSys Bandwidth Engine high density serial memory at 10 Gbps. For more information on the GigaChip Alliance, please visit
SiSoft and Xilinx Virtex-6 HXT FPGA at Booth #100
Xilinx will be showing the hardware correlation of the Virtex-6 HXT FPGA GTH transceiver IBIS-AMI model.
Agilent and Xilinx Virtex-6 HXT FPGA demo at Booth #201
Xilinx will be demonstrating the Virtex-6 HXT FPGA with the industry's lowest-jitter 11Gbps+ serial transceiver being analyzed by an Agilent DCA-X Digital Communications Analyzer.
For more information on Virtex-6 HXT FPGAs, please visit www.xilinx.com/products/virtex6/hxt.htm.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.