When asked whether further problems might emerge implementing the corrected design on the same wafer stock or with fresh wafers, Smith said: "We are very confident we understand the issue. Once we looked there it was very clear to our engineers what needed to change. We can implement that change by deleting and it is very straightforward and very high confidence."
Smith added: "This is not a functional issue with the chipset. In fact it is a degradation that is statistical in nature." This helps explain why the chip passed function tests at both Intel and OEMs and was able to get into production.
"Think of a single-digit percent of units may degrade and we could observe this functional issue occurring over the say the 3-year nominal lifetime of a notebook. So the first thing is this passed all our rigorous functional testing for many months internally and in fact it passed the rigorous testing of all our OEMs but as the number of samples grew, more than 100,000 of them are sent out, we get a few OEM returns. We confirmed one of those sightings early last week."
Intel brought a crash team together to evaluate the bug and determine the corrective action to be taken which resulted in the decision Sunday night (Jan. 30) to suspend Series 6 chip deliveries.
Smith said that to the best of Intel's knowledge there has not been a single consumer return or report of a system with this issue.
When pressed as to how an error could show up for a user Smith said that the BER (bit-error rate) would go up over time and could go so high that the serial-ATA port does not operate at all. Things could be worse or manifest sooner if a channel was used more than if it was used less, he acknowledged. He added that the companion chip helps enable six S-ATA ports and four are affected by the bug, while two ar not.