SAN FRANCISCO - At this week’s International Solid-State Circuit Conference (ISSCC) here, IMEC and Renesas Electronics Corp. presented a paper on a highly-linear reconfigurable transceiver that eliminates the need for surface acoustic wave (SAW) filters.
The approach is said to be a breakthrough towards fully reconfigurable radios by relaxing the requirements of the antenna filters, which suffer today from limited flexibility due to the high filtering specs. The fully reconfigurable transceiver, dubbed Scaldio, is compatible with multiple wireless standards, including the fourth generation mobile broadband standard 3GPP-LTE.
The reconfigurable receiver and transmitter technology is suitable for mobile handsets and all kind of battery-powered wireless connectivity devices, as well as for base-stations for small cells, and can be programmed to meet the requirements for many standards and dedicated needs.
''With 3dB noise figure and capable of handling a 0dBm blocker at 20MHz offset, the receiver has the highest blocker resilience for low noise figures. The fully reconfigurable receiver also achieves the highest linearity (+10dBm IIP3, +70dBm IIP2), and frequency range reported up to now and handles blockers well in any mode,'' according to IMEC and Renesas.
''The transmitter combines adaptive out-of-band noise filtering with voltage-sampling up-conversion to achieve RX band noise down to -162dBc/Hz allowing also here SAW-less operation,'' according to the paper. ''SAW-less transmitters become more and more important with the evolution towards future standards such as 3GPP-LTE where transmitters will need to operate in multiple FDD (frequency division duplex) bands.''
Yoshinobu Nakagome, associate general manager of the Mixed Signal Core Development Division Technology Development Unit at Renesas, said: “This accomplishment is an important step towards our integrated RF solution for next generation multimode wireless communication systems.''
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.