SAN FRANCISCO – After some debate, there is finally some consensus at the 22-/20-nm logic node-at least among leading-edge foundries.
During a panel session at the 2011 International Solid-State Circuits Conference (ISSCC) here, IBM, Globalfoundries and TSMC all agreed that they would extend planar bulk CMOS to the 22-/20-nm node. In other words, don’t expect foundries to embrace FinFETs, fully depleted SOI, multi-gate transistors or other newfangled structures at 22-/20-nm.
Intel Corp., another member of the panel, is still keeping its cards close to the vest and did not reveal its transistor plans at 22-/20-nm.
Still, there were few surprises during the panel. All vendors agreed that the 22-/20-nm node would also make use of copper interconnects, high-k/metal gates and ultra low k. Leading-edge chip makers are stuck using today’s 193-nm immersion lithography with double patterning.
This is because extreme ultraviolet (EUV) lithography won’t be ready in time for this logic node. ASML Holding NV has recently shipped one pre-production EUV tool, reportedly to Samsung Electronics Co. Ltd. Throughput remains low and tool cost is astronomical.
''EUV is making progress,’’ said Mark Bohr, an Intel senior fellow and director of process architecture and integration, in an interview. ''It’s not ready for prime time.’’
Needless to say, the 22-/20-nm logic node will be challenging. Besides lithography, high-k integration, power consumption, variability and cost remain challenging at the node.
Bohr believes the separate design and manufacturing teams must work more closely in a concept he called co-optimization. ''Co-optimization needs to start earlier at the research phase,’’ he said.
In any case, Globalfoundries, IBM, Intel, TSMC and Samsung have announced some details about their upcoming 22-/20-nm processes. At present, leading-edge chip makers are using conventional bulk CMOS and planar transistor structures for the 32-/28-nm nodes and above. For years, chip makers have used bulk CMOS. It’s well understood, cheap and a safe technology.
But going forward at 22- and 16-nm, there are some who believe that bulk CMOS will run out of gas. At those nodes, there are a number of transistor candidates on the table: III-V, bulk CMOS, FinFET, FD-SOI, multi-gate, among others.
Some are pushing hard for one technology. Jockeying for position in the next-generation transistor race, the SOI Industry Consortium claims to have made more progress in bringing fully-depleted silicon-on-insulator (FD-SOI) technology for next-generation mobile products.
The consortium members-ARM, Globalfoundries, IBM, STMicroelectronics, Soitec, and CEA-Leti—have announced results of an assessment and characterization of FD-SOI, saying that the technology is viable for mobile and consumer devices at the 20-nm node and perhaps beyond.
But even IBM Corp. admits that bulk CMOS will be the key technology for 22-/20-nm. FD-SOI ''will not be ready in time’’ for that node, said Ghavam Shahidi, IBM Fellow and director of silicon technology for the T.J. Watson Research Center, during the panel.
Samsung Electronics Co. Ltd., one of the members of IBM’s ''fab club’’ or technology alliance, recently rolled out its 20-nm process, which is based on bulk CMOS.
At the ISSCC panel, Bill Liu, vice president of technology solutions at Globalfoundries Inc., also listed the various technologies that are expected to be adopted at 22-/20-nm: high-k/metal-gate; 193-nm immersion with double patterning, strain engineering, among others.
After pushing the gate-first high-k approach for the 32- and 28-nm nodes, IBM's technology partners will move to rival gate-last technology at the 20-nm node. IBM's partners include AMD, Globalfoundries, Samsung and others, all of which insisted that the gate-first approach was better-until now.
Intel, TSMC and others have embraced the gate-last approach.
Meanwhile, Liu said the key challenges for the 22-/20-nm node will be power, lithography, among others. ''At 22-nm, lithography will become more of a gating item,’’ Liu said. Using 193-nm with double patterning will force chip makers to use ''more restrictive design rules,’’ he said.
Min Cao, director of 20-nm development at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), believes power and variability will remain challenging. ''Power constrained designs drive Vcc scaling but (the problem is) that variability goes up,’’ he said.