SAN JOSE, Calif. – Japan has formed a consortium to propel the infrastructure for photomask and inspection gear in extreme ultraviolet (EUV) lithography.
The group in Japan is called EDEC, said Shang-Yi Chiang, senior vice president of R&D at Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), during a keynote at the SPIE Advanced Lithography conference here.
Chiang also addressed other issues during the keynote.Last year, chip-making consortium Sematech launched a similar consortium to develop metrology tools for detecting defects in advanced masks needed for EUV lithography. The new EUVL Mask Infrastructure (EMI) Partnership has drawn interest from several entities.
The chip-making consortium recently warned that there is still a major funding shortfall and a lack of mask inspection gear to enable EUV lithography. Intel and Samsung have also expressed concerned about the lack of metrology tools in EUV.
The EMI Partnership will address this metrology gap in phases by funding development of three metrology tools. First efforts will focus on enabling an enhanced EUV mask blank inspection capability by 2011, followed by development of an aerial imaging metrology system (AIMS) for EUV in 2013, and finally an EUV mask pattern inspection tool able to work at 16 nm by 2015.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.