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Intel: EUV late for 10-nm milestone

3/1/2011 02:02 AM EST
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resistion
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re: Intel: EUV late for 10-nm milestone
resistion   5/8/2011 3:08:22 AM
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Since companies need to make money with multiple patterning to continue funding EUV, they remove the last reason to pursue EUV.

docdivakar
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re: Intel: EUV late for 10-nm milestone
docdivakar   3/24/2011 7:42:03 PM
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OOOPS, I meant to say "exactly the same statement... two years ago" at SPIE Litho conference!! MP Divakar

docdivakar
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re: Intel: EUV late for 10-nm milestone
docdivakar   3/24/2011 7:40:03 PM
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@MarkLapedus: I heard exactly the same statement at the SPIE Lithography show: at 14-nm, Intel will continue to use 193-nm immersion, plus a double-patterning with pitch splitting. @unknown multiplier: I am with you on this; I remain skeptical about EUV by 2013. It may be delayed until 2015 or 2016. MP Divakar

resistion
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re: Intel: EUV late for 10-nm milestone
resistion   3/9/2011 3:16:48 PM
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Intel is really keen on defects, and the EUV inspection tools it wants are not available until 2015, so EUV would be late for 7 nm as well.

resistion
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re: Intel: EUV late for 10-nm milestone
resistion   3/9/2011 3:11:53 PM
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At 5 nm, a silicon atom is already about 5% of the linewidth, so the natural roughness is already prohibitive.

unknown multiplier
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re: Intel: EUV late for 10-nm milestone
unknown multiplier   3/9/2011 2:43:58 PM
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EUV definitely will not be ready by 2013, then they will say it's for 7 nm.

antonio.tosi
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re: Intel: EUV late for 10-nm milestone
antonio.tosi   3/2/2011 8:56:08 AM
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Hi! Just a curiosity: why do you say litho road map ends around 7 nm? Is there any physical barrier for that technology? Thanks.

pixies
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re: Intel: EUV late for 10-nm milestone
pixies   3/1/2011 10:29:21 PM
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The litho road map ends around 7 nm. Even if EUV can catch the 10 nm node, it will only going to be a two-generation tool, it will never justify the cost.

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