GRENOBLE — The Design Automation and Tests in Europe (DATE) Conference has opened its doors today (March 14, 2011) in Grenoble, France. Before you get to Alpexpo, have a look at EDA DesignLine's list of EDA products that will be introduced and showcased at the show.
The list will then be updated as new information arrives.
And, obviously, company names are presented in alphabetical order.
- Adicsys Design SAS
(Arcueil, France) has introduced Synthesizable Programmable Core Architect (SPC Architect), a toolset that is claimed to enable an easy and transparent insertion of programmable logic for ASICs, SoCs and silicon IPs in general.
SPC Architect is an under-the-hood engine that provides an automated transformation of RTL modules into functionally equivalent yet re-programmable cores. In addition to allowing the process being performed without knowledge of programmable logic, the generated cores achieve a100-percent compatibility and 100-percent integration within any standard cell based ASIC design flow, Adicsys noted.
- AgO Inc.
(Phoenix, Arizona) said it has extended its AnXplorer analog and RF circuit optimization with new algorithms to port circuits between similar technologies. The AnXplorer 2011.02 release is claimed to improve the productivity of designers willing to port an existing custom circuit to a similar technology.
AnXplorer can fit into commonly used design toolsets as it works with industry standard SPICE netlists and simulators. A designer can define an unsized circuit, with design variables, constraints and objectives.
AnXplorer will then generate an optimized, centered circuit that meets or exceeds the design objectives across all corners specified by the user. It is based on a new multi-algorithmic optimization strategy based on a genetic algorithm.
- Asygn SAS
(Montbonnot, France) said it has introduced Tactyle 2.0, a revision of its analog system-level time-domain simulator.
Plugging into standard analog design environments, Tactyle 2.0 addresses some of the most difficult verification issues in today’s analog designs: circuits too large for SPICE; widely spaced time constants; high selectivity; complex, mixed-signal situations; massively repeated subcircuits (for imaging and memories, for instance).
Tactyle 2.0 key enhancements:
• 4 x speed increase over Tactyle 1.x – benchmarks now show an average speed improvement of approximately 300x over standard VerilogA simulations.
• RF option, seamlessly allowing the efficient simulation of systems involving signals with widely differing frequency components, such as baseband modulation of an RF carrier.
• SC option, allowing Tactyle 2.0 to interface to a System C environment in order to, for example, co-simulate large digital systems in System C (such as processors, modulators, demodulators) with an Analog/Mixed-Signal sub-system in Tactyle 2.0.
• Improved support for buses, facilitating the capture of the digital portion of the Design Under Test.
• Full support for double and int data types, and also for the integration and derivative operations.
• Extensions to the Tactyle library, including a transformer, new analog-to-digital conversion components, and extra controlled sources.
- C -
- Coventor Inc.
(Cary, N.C.) has released SEMulator3D 2011, the latest version of its virtual fabrication software for semiconductor and MEMS process development organizations.
The SEMulator3D 2011 release is claimed to provide a three-fold performance boost in model building time and new robust 3D mesh generation capabilities that create silicon-accurate meshes for physics-based simulations used to optimize the performance and manufacturability of semiconductor and MEMS devices.
In addition, Coventor said it is providing the first release of SEMulator3D Reader, a downloadable interactive 3D model viewer that will streamline communications among process development team members and with suppliers and customers.