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DDR2/DDR3 memory controller calibration IP for ASICs and FPGAs

3/22/2011 07:34 PM EDT
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Max The Magnificent
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re: DDR2/DDR3 memory controller calibration IP for ASICs and FPGAs
Max The Magnificent   3/22/2011 7:43:08 PM
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In a moment I'm going to ping the folks at the various FPGA companies to see if they've heard about (or are already using) this technology...

Sanjib.A
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re: DDR2/DDR3 memory controller calibration IP for ASICs and FPGAs
Sanjib.A   3/23/2011 5:54:53 PM
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Hi Max, this is an interesting news! I would look forward to learn about what you found after talking to the folks in the FPGA companies?

Max The Magnificent
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re: DDR2/DDR3 memory controller calibration IP for ASICs and FPGAs
Max The Magnificent   3/23/2011 6:51:42 PM
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Hi there -- I pinged folks I know at all of the FPGA companies and asked them to pass a link to my article to their techno-weenie folks -- I've not heard anything back yet -- I'm not sure if this could be implemented in the FPGA as purely soft digital fabric controlling the analog PHY, or if the FPGA company would have to do stuff to the physical chip...

Sanjib.A
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re: DDR2/DDR3 memory controller calibration IP for ASICs and FPGAs
Sanjib.A   3/24/2011 4:22:45 AM
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Thank you Max! I'll continue to watch this space for any updates if you find any reply from the FPGA manufacturers.

KARTHIKSRINIVASA.Srinivasa
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re: DDR2/DDR3 memory controller calibration IP for ASICs and FPGAs
KARTHIKSRINIVASA.Srinivasa   3/24/2011 5:59:30 AM
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Xilinx supports self calibration for their memory controller IPs. Maybe other vendors support too.

DrFPGA
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re: DDR2/DDR3 memory controller calibration IP for ASICs and FPGAs
DrFPGA   3/24/2011 10:20:03 PM
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Does this apply to DDR3 as well? Can't really tell from the release. It would help if they listed some of the parameters they 'fine tune'. Good luck on hearing back from the FPGA guys. I'm sure their legal dept is now in the loop....

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