SAN JOSE, Calif. – Many wonder if mainstream 3-D chips based on through-silicon-via (TSV) technology is feasible-or will even fly-amid ongoing problems in the arena.
The progress remains slow and the technology still appears to be in the ''power point’’ stage.
Still, the IC industry is moving full speed ahead with a monumental and costly push to develop TSV-based 3-D chips. A plethora of companies, including IBM, Intel, Samsung, Toshiba, TSMC and others, are exploring the possibility of stacking current devices in a
At the 2011 GSA Memory Conference here on Thursday (March 31), four industry organizations-IMEC, ITRI, Sematech and SEMI-separately made presentations about the latest progress within their respective entities for 3-D chips based on TSV.
A 3-D working group within SEMI met for the first time this week to sketch out the initial wafer and tool standards for TSV technology. SEMI has three task groups within its 3-D group. A fourth group is being formed, which may be led by Applied Materials Inc.
In a separate program within Sematech, the chip-making consortium is expanding its own 3-D program. One surprising chip maker, Analog Devices Inc., is joining Sematech’s ''3-D Design Enablement Center.’’ Altera, LSI, On Semiconductor and Qualcomm are also part of the center.
A plethora of others are also scrambling to develop TSV-based technology-and for good reason: There are fears that IC scaling is becoming too costly for most chip makers-or will end in the distant future.
So instead of scaling, there is another concept on the table: stack and connect devices in a 3-D configuration using TSVs. For years, chip makers have been talking about 3-D chips based on TSVs. But except for select products-such as CMOS image sensors-the technology has not moved into the mainstream, due to costs, lack of standards and other factors.
In theory, 3-D chips could evolve in two steps. The first step is a 2.5-D scheme using silicon interposers. Then, eventually, the industry could move to TSV-if it can solve the multitude of problems with the technology.
Right now, there are several new and mainstream 3-D chip projects in the works. For example, Semtech Corp. is working with IBM Corp. and its 3-D TSV technology to develop a combination analog-to-digital converter and DSP platform. These two different technologies are connected through a single wiring layer on an interposer, which supports a bandwidth of greater than 1.3-Tbps.
Last year, Xilinx, Inc. announced the industry's first stacked silicon interconnect technology for delivering breakthrough capacity, bandwidth and power savings using multiple FPGA die in a single package for applications that require high-transistor and logic density. By embracing 3-D packaging technologies and TSV for its 28-nm 7 series FPGAs, Xilinx's can address systems with resource requirements that are more than double the reach of the largest single-die FPGAs. Initial devices will be available in the 2nd half of 2011.
In a separate effort, Hynix, Samsung and others have identified a new device vehicle that could propel TSV-based 3-D chips into the mainstream: a wide I/O DRAM for cell phones, tablets and related products.
Wide I/O, a memory interface standard in review at JEDEC, defines a 512-bit wide interface to increase the bandwidth between memory and logic. The interface operates at a peak data transfer rate of 12.8- gigabytes per second (GB/s), which is up to four times the performance of conventional low-power memory solutions.
Today, mobile DRAM is based on a technology called low-power double data rate 2 (LPDDR2). Beyond LPDDR2, Samsung and others are pushing wide I/O DRAM for mobile applications. Wide I/O will evolve in two phases. The first wide I/O DRAMs are four-partitioned devices, which will be stitched together via micobumps. They are expected to appear in 2013.
In the future, vendors hope to stack multiple wide I/O DRAMs using TSVs. Some say those devices will appear in 2014 or 2015. Some believe the technology will appear later than sooner. Due to the complexity and costs, TSV-based wide I/O DRAM will not arrive until ''the second half of the decade,’’ said Sharon Holt, senior vice president and general manager of the Semiconductor Business Group at Rambus Inc.
Holt also does not believe the industry will directly migrate from LPDDR2 mobile DRAM to wide I/O DRAM. LPDDR2 mobile DRAMs began shipping last year, but wide I/O DRAM will not appear for some time.
As a result, there is a time gap between the two technologies. Not surprisingly, Rambus is pushing mobile XDR, one of the many next-generation mobile DRAM technologies in the market.
I think it should be realized that 3DIC technology is fundamentally a packaging technology not semiconductor. TSV adds the extra semiconductor and thermal/stress complexity and the close mutual infringement of semiconductor and packaging players. There also has to be a controller die "one to rule them all" to manage all the vertical connections. But the sequential nature of stacking makes the flexibility not obvious.
To unknown multiplier: good point. But I still claim that silicon penalty is negligible considering benefits. You would loose more yield and silicon by designing very large IC instead of few smaller ones connected in 3D thru TSV. The challenge is to make this technology manufacturable in large volume...Kris
As said above, currently 10 um or less is easily envisioned but not achieved in the final package.
A smaller TSV would become more resistive, defeating its original purpose. So you have to thin down the silicon, another big change.
The smaller TSVs are via first. I am not sure they will be the final chosen route, due to process issues. Via last seems to be the more conservative choice, and has dimensions in the high tens of microns currently.
To @docdivikar, thank you, I thought that you could easily do 5um via so 10 sq mm area penalty looked really suspicious...if industry can get down to 1um I don't think we have to worry that much about silicon space loss...
perhaps someone would be interested in talking about these challenges at CMOS Emerging Technologies meeting? www.cmoset.com, firstname.lastname@example.org
@yalanand: GSA has also been leading the effort on 3D IC Standardization (led by Herb Reiter; I am part of the standards committee) in addition to SEMI & Sematech. GSA had an excellent 3D Roadshow presentations at the DAC 2010 where a number of companies presented their work. There is going to be another one this year at DAC San Diego.
@greenpattern: temperature concerns are certainly NOT glossed over by the companies working on 3D. Accompanying thermomechanical stresses and its transport through TSV's (thermo- & stress-migration) are equally important and are being rigorously studied to generate rules for design.
@iniewski: yes, there is something off in @@resistion's math -the 5u TSV's are in production today, with roadmaps already being talked about to 2u & 1u. But there is a genuine concern regarding keepouts & area penalties but those are drowned out by the benefits 3D stacking provides.
TSV's have come a long way from few years ago when they were only brewing a storm in a tea cup!
Dr. MP Divakar
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