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Momentum builds for 3-D chips

4/2/2011 05:55 AM EDT
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greenpattern
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re: Momentum builds for 3-D chips
greenpattern   4/17/2011 4:38:11 AM
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I think it should be realized that 3DIC technology is fundamentally a packaging technology not semiconductor. TSV adds the extra semiconductor and thermal/stress complexity and the close mutual infringement of semiconductor and packaging players. There also has to be a controller die "one to rule them all" to manage all the vertical connections. But the sequential nature of stacking makes the flexibility not obvious.

krisi
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re: Momentum builds for 3-D chips
krisi   4/9/2011 8:35:18 PM
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To unknown multiplier: good point. But I still claim that silicon penalty is negligible considering benefits. You would loose more yield and silicon by designing very large IC instead of few smaller ones connected in 3D thru TSV. The challenge is to make this technology manufacturable in large volume...Kris

KB3001
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re: Momentum builds for 3-D chips
KB3001   4/9/2011 3:30:38 PM
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Certainly that's the most promising scenario, but we have to wait until it becomes economical to do so.

unknown multiplier
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re: Momentum builds for 3-D chips
unknown multiplier   4/9/2011 2:14:09 PM
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If the TSV has to go through several wafers as a direct link between top and bottom, it constitutes unusable area for the wafers in between.

resistion
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re: Momentum builds for 3-D chips
resistion   4/6/2011 8:09:37 PM
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As said above, currently 10 um or less is easily envisioned but not achieved in the final package. A smaller TSV would become more resistive, defeating its original purpose. So you have to thin down the silicon, another big change.

resistion
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re: Momentum builds for 3-D chips
resistion   4/6/2011 8:07:44 PM
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The smaller TSVs are via first. I am not sure they will be the final chosen route, due to process issues. Via last seems to be the more conservative choice, and has dimensions in the high tens of microns currently.

resistion
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re: Momentum builds for 3-D chips
resistion   4/6/2011 8:02:24 PM
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I was using 100 um pitch, the TSV can be any size within it, and you can also take into account the keep out area as well. Most examples I saw were 30 um or so.

krisi
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re: Momentum builds for 3-D chips
krisi   4/6/2011 6:50:21 PM
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To @docdivikar, thank you, I thought that you could easily do 5um via so 10 sq mm area penalty looked really suspicious...if industry can get down to 1um I don't think we have to worry that much about silicon space loss... perhaps someone would be interested in talking about these challenges at CMOS Emerging Technologies meeting? www.cmoset.com, kris.iniewski@gmail.com

docdivakar
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re: Momentum builds for 3-D chips
docdivakar   4/6/2011 6:19:59 PM
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@yalanand: GSA has also been leading the effort on 3D IC Standardization (led by Herb Reiter; I am part of the standards committee) in addition to SEMI & Sematech. GSA had an excellent 3D Roadshow presentations at the DAC 2010 where a number of companies presented their work. There is going to be another one this year at DAC San Diego. @greenpattern: temperature concerns are certainly NOT glossed over by the companies working on 3D. Accompanying thermomechanical stresses and its transport through TSV's (thermo- & stress-migration) are equally important and are being rigorously studied to generate rules for design. @iniewski: yes, there is something off in @@resistion's math -the 5u TSV's are in production today, with roadmaps already being talked about to 2u & 1u. But there is a genuine concern regarding keepouts & area penalties but those are drowned out by the benefits 3D stacking provides. TSV's have come a long way from few years ago when they were only brewing a storm in a tea cup! Dr. MP Divakar

krisi
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re: Momentum builds for 3-D chips
krisi   4/5/2011 10:47:38 PM
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To @resistion, how did you get 10 sq mm? I though TSV vias are not that large...Kris

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