LONDON – Genasic Design Systems Ltd., a privately-held fabless RF design company formed in 2009, has announced the availability of its first chip, a 65-nm CMOS transceiver IC for HSPA and LTE applications.
The GEN4100 has dual receive and transmit chains enabling full MIMO operation in both transmit and receive. The company states that the IC has "low power consumption" making it suitable for use in handsets and dongles, as well as in 3G and 4G femtocell basestations. But the company does not quantify the power consumption. A data sheet is available on application the company states.
Genasic (Riseley, England) was founded by Ashok Dhuna who serves as CEO. Dhuna was vice president of RF engineering at Sequans. Prior to that he was chief technology officer and founder of Synad Technologies Ltd.; a wirelss LAN chip company sold to STMicroelectronics in 2003 for an undisclosed amount. The company offers design services and claims to have completed a number of LTE designs.
Dhuna's experience covers numerous mobile communications technologies including GSM, Wi-Fi, WiMax and LTE. Genasic's vice president of business development is Mike Baker who was co-founder and CEO of Synad. Genasic's vice president of engineering is Hassan Shafeeu. He was an RF IC engineer and design manager at Synad and led a team responsible implementing both 2.5 and 3.5-GHz RFIC designs at Sequans.
The GEN4100 operates from 680- to 2700-MHz with channel bandwidths programmable between 1.4- and 20-MHz. It has three receive ports between 1700 and 2700-MHz and two receive ports between 680 and 1500-MHz. There is one transmit port in the each of the upper and lower bands.
The chip is packaged in a 9.8-mm by 8.6-mm thermal leadless array package with a ball-pitch of 0.4-mm. It can be provided as a discrete packaged device, as a bare die for inclusion in multi-chip modules or as hard-macro for integration in a system-on-chip.
The company did not say what foundry it is using to manufacture the GEN4100. But is says that it has worked with all the major foundries for the processing of devices.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.