SAN FRANCISCO—EDA and IP supplier Cadence Design Systems Inc. Monday (April 11) announced a comprehensive DDR4 intellectual property (IP) solution said to enable SoC designers to immediately take advantage of the performance gains offered by DDR4, the fourth-generation double-data-rate synchronous DRAM standard.
Cadence (San Jose, Calif.), which last year acquired IP vendor Denali Software Inc. for $315 million, said it has worked with hundreds of customer to integrate previous versions of the DDR memory controller interface. The Cadence DDR4 solution includes hard and soft PHY IP, controller IP, memory models, verification IP, tools and methodologies and signal integrity reference designs for the package and board.
According to Neil Hand, group director of marketing for Cadence's SoC Realization group, SoC designers are increasingly embracing third-party IP for memory storage. Hand said he views the transition as stage three of the IP market evolution. In the 1990s, designers began to embrace third-party processor IP, then began embracing interface IP in the 2000s. The embrace of memory and storage IP, which began in earnest last year, is the third wave, he said.
"Memory and storage is the new frontier for IP," Hand said. "It is becoming a more complicated area for customers and it really touches every area of the design."
According to Hand, it wasn't long ago that designers thought the only form of IP worth using was the processor. "Now it's just a given that if you start your own design you're not going to build your own PCI Express interface," Hand said. "Soon it will be that way with memory and storage as well."
According to Cadence, IP adoption has entered the "final frontier," when designers will increasingly use IP for memory and storage. Source: Cadence.
Given the impact that memory controller IP has on the overall performance of the SoC and system, Cadence said it is expanding the in-house development of comprehensive memory and storage controller IP to ensure maximum robustness and performance. The company said it plans to continue Denali's tradition of developing IP in parallel with industry standards, to give customers a leg up in time to market.
If you get your memory and storage architecture right, you're design can meet its needs," Hand said. "If you get it wrong, it will impact the entire design. If you get it wrong, the SoC is dead."
The DDR4 specification, an SDRAM memory technology standard currently under review at Jedec, proposes speeds ranging from 1,600 mega transfers per second (MT/s) up to 3,200 MT/s, more than 50 percent faster than the current DDR3 standard. As the standard evolves to support higher frequencies and throughput, signal integrity, power and performance issues multiply, according to Cadence. The specification is expected to be finalized this year.
Cadence said its IP integration environment enables customers to model and analyze their target memory topology, and verify the behavior of the IP at both the SoC and system levels. The soft PHY and controller provide tremendous flexibility and can be synthesized to support the full range of frequencies and voltages, Cadence said. Designers can deliver either a pure DDR4 SoC, or combine DDR4 with other technologies like DDR3 or LPDDR2, Cadence said.
For interface IP, Cadence said it would offer high-performance interface solutions, such as PCI Express Gen2 and Gen3, as well as Gibabit Ethernet (GbE), 10 GbE and 40 GbE solutions. The combined Denali and Cadence services team offers decades of design expertise, the company said.
For compute IP, Cadence said it would continue to collaborate with leading IP providers such as ARM Holdings plc to ensure that the company can support the compute needs of SoC designers. The group's primary focus will be on ensuring successful integration through advanced methodologies, tools and reference flows that take a holistic approach to SoC design and verification, Cadence said.
Cadence said its DDR4 controller IP, verification IP and memory models are available now, supported by both Cadence and third-party design tools and methodologies. A soft DDR4 PHY is expected to be available this quarter, while a hard PHY solution for 28-nm TSMC geometries is expected to be available by the third quarter, Cadence said.
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