Apple Inc.'s iPad2 has only been publicly available for about a month. However, it appears this young device has kept few secrets since we have known there were 21 magnets in the smart cover and saw a die floorplan of the A5 within mere days of its release. The flurry of the first wave of disassembly and dissection seems to have died down while we might assume that some very detailed circuit analysis is likely just beginning to be scoped out.
When the A4 was subjected to the same procedure just under one year ago, there was a sense it was going to underwhelm anyone expecting a unique design because so little time had passed between Apple ramping up its design team with the acquisition of PA Semi and the release date. There simply wasn't time to generate a new design. The A5 is a different story. Another year has passed.
The A5 is also the second data point in terms of design strategy for Apple's iOS SoC. While two data points constitute a streak only in baseball, this second design would have had sufficient time for Apple to be moving in the direction they want. So how did the A5 fare? Has it met expectations at this early stage of the analysis?
First, a look back
During the Jan. 27, 2010, keynote both the iPad and A4 were publicly debuted for the first time. While the former has become a media darling and the object of global consumer desire, the latter quietly went about its business filling more and more sockets.
During 2010 the A4 appeared in the iPhone 4, iPod Touch and Apple TV. Although the A4 played second fiddle to the iPad, it did just fine in its own right. Yes it is not Apple's first design effort, but it is arguably their most important with the A4 being central to Apple's iOS devices and therefore key to a very large revenue stream for the largest technology company, something that cannot be said of previous design efforts.
While the client is somewhat captive in this case it is worth considering the A4 and now A5 as a semiconductor story. We might be jumping the gun to call them rivals, but other semiconductor companies are certainly taking the A-series of SoCs seriously because of the sheer number of sockets and high revenues those products generate.
At the time the A4 was announced, the burning question was how much of the design could be attributed to acquired design teams, especially PA Semi since they had been inside Apple longest. With an over-abundance of rumors by the time the A4 was available to the public, it was important to collate the physical evidence. Thus, our last look at the A4 consolidated some existing reverse engineering information, seasoned it with our own, and contemplated whether there was evidence of circuit design originating from Apple's PA Semi and Intrinsity acquisitions.
One conclusion was that there was evidence of Intrinsity design. We also concluded that the A4, on the block level, was very similar to Samsung's S5PC110. At that point the A4 did not appear all that unique. The simple finding that there were only two circuit blocks different between the A4 and S5PC110 spoke strongly to existing IP relationships.
The A5 should be different. Apple has had more time and Samsung has migrated to the Tegra 2 for their Galaxy 10.1.
Agreed. With both A4 and A5 on same node and A5 much larger than A4 while iPad still maintaining similar battery life. It certainly seems Apple has exploited clever hardware+software exploitation. It is still relatively hard for rivals to do that in current form (perhaps future close partnerships arise for Android+Samsung, Microsoft+Nokia :)).
Apple becoming involved in semi-design to higher degree will certainly give them flexibility and may result in an ongoing strategic advantage.
A lot more understanding could have added in the article by comparing it to other ARM Cortex A9 processors on 45nm silicon like OMAP4;
Just looking at the block diagram and comparing it to A5 would tell you alot.
You could have discussed differences in size between PowerVR SGX543MP2 in A5 and PowerVR SGX540 in OMAP4;
Even ARM's site itself provides info on example die sizes with different process for development kit chips that give some insight on what to expect.
Cortex A8 supported optional upto 1MB of L2 Cache while A9 supports upto 8MB for example.
Here is an interesting quote;
"A final mobile constraint that must be addressed is balancing the need to minimize die size, but providing large enough memory cache to keep multiple cores from being stalled. If a single core device requires
N amount of cache, up to 4*N cache may be required to achieve good performance in a multicore device.
Other memory design issues include data coherence and system memory consistency, to ensure processors
all have access to the current data at the correct time"
See Page 3;
Some more general information from other chip makers of ARM designs would have provided more insight.
Sure there are lots of different IP blocks to choose from and it is important to have designer level understanding to make right choices.
But Apple has nothing to gain making IP choices or custom development public public it is not selling chips. Apple can also benefit from the "magic" of people imagining they are doing much more than they actually are.
It would be good to compare A5 to the other Top 3 SOCs; Has EE times ever done a disection of the Atom Processor ? Why would Apple tout the A5 ? An Ideas for future article:
Can the A5 architecture be implemented in a 28 nm FPGA [Altera, Xilinx, Archonix] with similar performance and cost ?
What a way to squander the PA-SEMI acquisition (their lead design team has almost entirely jumped ship)and the their PA6T architecture. Rather than unify their entire product range under a single, modern ISA (PowerPC) Apple elected to fragment it with ARM, PowerPC and x86. And to add insult to injury, ARM's Neon SIMD ISA is just woeful compared to VMX or even SSE.
When the A4 came out there was speculation that it would not support cameras because they were not included in iPad. Then iPhone 4 had two cameras and an A4. While not touching on this thread in the article I suspect the same. There is likely an "upgrade cycle" lurking in there somewhere.
David Patterson, known for his pioneering research that led to RAID, clusters and more, is part of a team at UC Berkeley that recently made its RISC-V processor architecture an open source hardware offering. We talk with Patterson and one of his colleagues behind the effort about the opportunities they see, what new kinds of designs they hope to enable and what it means for today’s commercial processor giants such as Intel, ARM and Imagination Technologies.