PORTLAND, Ore.—Next generation trends in the physical fabrication of semiconductors, including 3-D and maskless lithography, were recently laid out at this year's 20th annual International Symposium on Physical Design (ISPD 201) in Santa Barbara, Calif., sponsored by the Association for Computing Machinery.
New this year is an annual award to honor the past contributions of the movers and shakers in physical design of advanced semicondutors.
"Starting this year, ISPD will initiate another tradition [in addition the annual design contest] by introducing commemorative sessions to honor respected pioneers in the physical design (PD) field, to trace their contributions in shaping the PD landscape, to explore future directions following their footsteps," said Yao-Wen Chang, a professor at National Taiwan University and general chair of ISPD 2011.
The first recipient of the annual ISPD award commemorates the many electronic design automation (EDA) contributions of Phil Kaufman Awardee and former Cadence board member Ernest Kuh, an EDA pioneer involved in the development of the first Spice simulator and former dean of engineering at the University of California, Berkeley.
The annual design contest this year concentrated on the global routing congestion problems that plague lithographic placement algorithms below the 65-nanometer node. Instead of judging placement algorithms based on wire length or spreading capabilities, as in past years, the contest this year used "routability" as its evaluation metric. As the "gold standard" in routability, "coalesCgrip" by researcher Hamid Shojaei in the lab of University of Wisconsin professor Azadeh Davoodi was used to judge the contest.
Contest chair Natarajan Viswanathan, a researcher in the Systems and Technology Group at IBM Austin Research Laboratory, managed the contest, which posed eight challenging industrial benchmarks to each team to test the routability of their placement algorithms. First place went to "Ripple," developed by a team in the lab of professor Evangeline Young at the Chinese University in Hong Kong, doctoral candidates Xu He, Tao Huang, Linfu Xiao, Haitong Tian and Guxin Cui.
Second place went to "mPL11" developed by a team from the lab of professor Jason Cong at the University of California at Los Angeles, third place went to "SimPLR" from the lab of professor Igor Markov at the University of Michigan. Fourth place went to "RADIANT," developed in the lab of professor Yao-Wen Chang at National Taiwan University.
Best paper this year went to professor David Pan and researcher Kun Yuan at the University of Texas (Austin), for their innovative adaptation of e-beam lithography to production environments. Today, e-beam lithography is mostly used for prototyping, since it is too slow for cost effective volume manufacturing of semiconductors. But Pan and Yuan argue that e-beam can compete with the increasingly expensive masks used for double, triple or even quadruple exposure lithography. Pan and Yuan recommend using the stencil planning and optimization algorithms described in their paper to speed up e-beam lithography for production environments.
As double, triple and
quadruple patterning increases the cost of masks at 32 nanometer and
below, maskless electron-beam lithography can cut costs by imaging
wafers through a shaping aperture and character stencil. Source: University of Texas (Austin), Kun Yuan and David Pan.
Also this year, innovative "computational lithography" for moving below 22-nanometers as well as 3-D interconnection techniques for "terascale computing" were described by Intel Labs, Tezzaron Semiconductor and others. For instance, Intel Fellow Vivek Singh described multi-mask patterning, pixilated masks and other computational lithography techniques that will be key to Intel's move to the 14-nanometer node, according to Singh.
Intel researcher Tanay Karnik described floor-planning, power routing, input/output circuits, test and assembly of 3-D processors stacked on DRAM. And Bob Patti, chieftechnology officer of Tezzaron Semiconductor, gave a side-by-side comparison of the improvements enabled by 3-D chip stacking, including 40 percent power reduction, a four-times density increase, over 300 percent performance boost, and 50 percent cost reduction.
Processors can attain the terascale,
according to Intel Labs, by stacking processors with on-chip mesh
connectivity on top of memory chips inside the same package. Source: Intel.