SAN FRANCISCO—EDA vendor Cadence Design Systems Inc. Monday (April 25) introduced the latest version of its Allegro PCB and IC packaging technology, delivering new capabilities that the company says provide increases in productivity and predictability across silicon, SoC and system development.
New technologies in Allegro 16.5 include advanced miniaturization capabilities, integrated power delivery network analysis, DDR3 design-in kit, bolstered co-design featured and flexible team-design enablement to address global designer productivity, Cadence (San Jose, Calif.) said. The company also announced that the Allegro 16.5 technology will be available through product configuration that enables users to access advanced features on-demand for specific design tasks, thus optimizing total cost-of-ownership.
The new Allegro 16.5 features and capabilities are aimed at easing the path to co-design and analysis between engineers involved in Silicon, SoC, and System Realization, and enabling more predictable and efficient design flows that deliver higher-quality end products, Cadence said.
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