SAN JOSE, Calif. - The Silicon Integration Initiative (Si2), an organization focused on the development and adoption of standards to improve IC design, is quietly forming a standards group for 3-D chips.
The so-called Open3D Project will enable interoperable 2.5-D/3-D design and EDA flows with open standards, according to Si2.
Over a dozen companies are interested in the effort, which hopes to devise standards for 3-D chips based on through-silicon vias (TSVs), according to Si2. Si2 is an organization of industry-leading companies in the semiconductor, electronic systems and EDA tool industries.
The plan is to have a ''kickoff meeting'' at the upcoming Design Automation Conference (DAC) In San Diego, the group said. DAC will be held June 5-9. The goal is to set the initial standards by Q1 of 2012.
Still, a plethora of others are also scrambling to develop TSV-based technology-and for good reason: There are fears that IC scaling is becoming too costly for most chip makers-or will end in the distant future.
So instead of scaling, there is another concept on the table: stack and connect existing devices in a 3-D configuration using TSVs. For years, chip makers have been talking about 3-D chips based on TSVs. But except for select products-such as CMOS image sensors-the technology has not moved into the mainstream, due to costs, lack of standards and other factors.
In theory, 3-D chips could evolve in two steps. The first step is a 2.5-D scheme using silicon interposers. Then, eventually, the industry could move to 3-D TSV-if it can solve the multitude of problems with the technology.
Ultimately, the subcontractors will join forces with the foundries in TSVs. Working with foundries, the subcontractors will provide wafer thinning and other services in what is called a ''via-mid’’ process.
Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is working with ASE and other subcontractors in the arena. Last year, Elpida Memory Inc., Powertech Technology Inc. and United Microelectronics Corp. (UMC) formed an alliance to speed up the development of 3-D chips at the 28-nm node as well as other processes.
Standards are a key in the arena. A 3-D working group within SEMI recently met for the first time this week to sketch out the initial wafer and tool standards for TSV technology.
Chip research consortium Sematech this week announcedthat six semiconductor companies have joined its 3-D enablement program based at the College of Nanoscale Science and Engineering (CNSE) of the University at Albany.
The six companies are Advanced Semiconductor Engineering Inc. (ASE), Altera Corp. Analog Devices Inc. (ADI), LSI Corp. and On Semiconductor Corp. and Qualcomm Inc. They join Globalfoundries, Hewlett Packard, Hynix, IBM, Intel, Samsung, and UMC in a broad initiative preparing for through-silicon via (TSV) enabled 3-D stacked components.
@unknown multiplier: there is minimal impact on the PCB developers by 3D TSV technology. In fact, 3D TSV's help alleviate the routing congestion on the PCB/motherboards as the number of I/O's in the package are increasing. A prime example would be an FPGA for 100Gig/40Gig motherboards -with differential signaling and the 12-lane transmit/receive (and the required grounds to isolate signals), this is going to choke the board design. So some functions of the boards including power management can be answered effectively by 2.5D/3D option.
On an energy consumption level, 3D/2.5D makes sense. In fact, the joule/bit metric is ages apart from side-by-side on the motherboard vs. 3D stacked/2.5D stacked/lateral designs in favor of the latter.
Dr. MP Divakar
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