SAN FRANCISCO - As expected, Intel Corp. Wednesday (May 4) rolled out its 22-nm process—with a twist.
The chip giant introduced the process, based on its long-awaited 3-D transistor design, dubbed tri-gate. First disclosed by Intel in 2002, the tri-gate transistor will form the basis of its 22-nm node. Intel also demonstrated the world's first 22-nm microprocessor, codenamed Ivy Bridge.
Ivy Bridge-based Core family processors will be the first high-volume chips to use tri-gate transistors. Ivy Bridge is slated for high-volume production readiness by the end of this year.
But missing from the announcement was a 22-nm mobile processor, which could fend off competitive threats from the ARM camp.
Intel's 22-nm process will also be based on Intel's third-generation high-k/metal-gate scheme. It will also use copper interconnects, strain silicon and other features. Like 32-nm, Intel will make use of 193-nm immersion lithography.
Intel did not disclose any details about the low-k interconnect technology. Intel insists that it will not use silicon-on-insulator (SOI) technology. SOI wafers will add about 10 percent to total process cost, according to Intel.
The tri-gate transistor represents a major shift in the IC industry. For decades, the industry has used the traditional "flat" two-dimensional planar gate. Intel seeks to replace the planar gate with a thin three-dimensional silicon fin that rises up vertically from the silicon substrate.
Other leading-edge chip makers are looking at multi-gate transistor structures, including IBM’s fab club, TSMC, among others. The tri-gate transistor technology is known outside Intel as a FinFET. One company, TSMC, plans to roll out its initial FinFETs at the 14-nm node.
In any case, Intel will have at least a ''three year lead’’ in the multi-gate transistor race, said Mark Bohr, an Intel senior fellow and director of process architecture and integration, at a press event here. Bohr said the tri-gate technology can scale to the 14-nm node, but he stopped short of talking about the next node after 22-nm.
The chip giant calls its technology a ''fully depleted tri-gate transistor. Tri-gate transistors form conducting channels on three sides of a vertical fin structure, providing 'fully depleted’ operation.''
"Control of current is accomplished by implementing a gate on each of the three sides of the fin—two on each side and one across the top—rather than just one on top, as is the case with the 2-D planar transistor," according to Intel. "The additional control enables as much transistor current flowing as possible when the transistor is in the 'on' state (for performance), and as close to zero as possible when it is in the 'off' state (to minimize power), and enables the transistor to switch very quickly between the two states (again, for performance)."
The 22-nm tri-gate transistor provides up to 37 percent performance increase at low voltage versus Intel's 32-nm planar transistors, the company said. This gain means that they are ideal for use in small handheld devices, which operate using less energy to "switch" back and forth, according to the company. Alternatively, the new transistors consume less than half the power when at the same performance as 2-D planar transistors on 32-nm chips.
To enable 22-nm, Intel must do a ''couple more’’ double patterning steps, Bohr said. But in all, the company will use standard fab tools in the technology and the process cost adder is
only 2 to 3 percent.
The 22-nm process is called 1270 and it is starting to ramp. First wafers will come out of D1D in Oregon and then volume production will start at F32 in Arizona in the latter half of this year, Intel said.
Intel, which last year surprised semiconductor industry observers by agreeing to serve as a foundry provider for programmable logic startup Achronix Semiconductor Corp., has apparently agreed to a similar arrangement with another up-and-coming programmable logic startup, Tabula Inc., according to reports. Intel has declined to comment on the Tabula reports, which a spokesperson termed a rumor.
On Monday, Piper Jaffray analysts said they believe that Intel is vying to land Apple Inc.'s foundry business.
Analysts had mixed feelings about Intel's 22-nm tri-gate announcement. ''The performance numbers are impressive,’’ according to analyst Doug Freedman of Gleacher & Co.
''This only adds 2-3 percent to finished wafer costs vs. planar technology (to produce the silicon 'fin' that creates a 3D transistor channel and gate, which provides better scaling factor than planar technology - likely more than offsetting the extra cost with die size benefits),'' he said. ''Tri-gate can be tuned to lower leakage (fully depleted transistors) or lower threshold voltage. The bottom line is this is much better for performance at low-power/low-voltage operation, as the shutdown process is key to total power consumption.''
Intel is targeting the first 22-nm product in the desktop/server space, but Freedman believes the chip giant should initially look at another segment . ‘’Why not the mobile first?’’ he asked.