SAN FRANCISCO—Chip foundry giant Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) is tightening its collaboration with EDA vendor Cadence Design Systems Inc. around design-for-manufacturing (DFM) and taking a step back from what many consider EDA turf, according to an announcement by Cadence Monday (May 9).
Under the new collaboration, Cadence (San Jose, Calif.) said it would offer TSMC customers DFM expertise and technology in a service model. TSMC, which requires that customers provide lithography and planarity analysis for designs at 45-nm and below, will scale back its own DFM services offerings, instead referring customers to Cadence.
Manoj Chacko, director of product marketing at Cadence, said TSMC would continue to jointly review analysis results with Cadence. For customers, the process will be much as it was before, except that they will interact with Cadence employees rather than TSMC, Chacko said.
"They can think of us as an extended arm of the TSMC DFM services," Chacko said.
For now, Cadence is the only vendor certified by TSMC to provide DFM services to TSMC customers. But Chacko said at the recent TSMC Technology Symposium TSMC executives said other vendors—presumably Synopsys Inc. and Mentor Graphics Corp.—would be certified late this year.
Chacko acknowledged that the certification should represent a significant business opportunity for Cadence—particularly until the company's rivals in EDA receive the same certification. Chacko declined to say how much revenue Cadence expects to generate from DFM services for TSMC customers. Asked how many employees would be assigned to Cadence DFM Services, Chacko declined to give a number but described the unit's staffing as "comprehensive."
TSMC's decision to scale back its own DFM services and refer customers to EDA vendors represents a pullback from what many considered the foundry giant's encroachment into EDA territory. In recent years some have pointed to TSMC's DFM service offerings as an indication that the company might get more involved in offering customers EDA services and tools.
"In my opinion, I don't see them [TSMC] getting into EDA territory," Chacko said. "I see them being ahead with collaborating and building structure."
Cadence said its DFM Services group would offer model-based simulation of lithography process checks and virtual chemical mechanical polishing (CMP) for TSMC 40-nanometer technology and below. The goal is to enable design teams to effectively get help in detecting litho or CMP hotspots in order to fix them prior to tapeout, Cadence said.
"At 40 nanometers and below, it is essential that design teams take DFM issues into account throughout the design process," said Suk Lee, director of design infrastructure marketing at TSMC. "DFM services from Cadence are a key milestone of our long-term collaboration with Cadence to help our common customers to address critical design needs in advanced technologies."
Cadence DFM Services will provide TSMC customers with turnkey access to DFM analysis based on TSMC’s DFM data kitensure needed accuracy, and DFM Services output analysis reports, which enable fixing in Cadence's Encounter Digital Implementation System or Virtuoso custom/analog implementation technologies, Cadence said. Cadence DFM Services also offer a scalable and secured IT infrastructure that helps reduce the risk of schedule slips while optimizing time to volume, according to the company.
Cadence and TSMC have for years collaborated in many areas, including DFM technology.