SAN JOSE, Calif. – PMC-Sierra has jumped into the market for 40G coherent optical transceivers, one day after startup ClariPhy revealed its progress on a similar part. The Polo 40G chip is part of the first wave of silicon for next-generation 40 and 100 Gbit/s carrier networks.
The company claims its 16W chip supports transmissions over 25 percent greater distances than competing devices thanks to the company's proprietary Swizzle forward error correction. The 40nm CMOS part aims to accelerate the deployment of fast metro, regional and long-haul networks.
Nortel Networks was the first to implement coherent optical networks, modulating multiple data streams on a single wavelength. However first generation systems required multiple line cards packed with ASICs and FPGAs.
"People only deployed 40G if they had to because it wasn’t cost or power efficient," said Daryn Lau, general manager of PMC's communications products division. But now with CMOS chips integrating DSP and mixed-signal functions multiple transceivers can be packed on a line card and "it's cheaper on a per-bit basis to deploy 40G," he said.
Long haul designs can pack one or two ports on a line card that serves distances up to 3,200 kilometers. Line cards for metro nets may be able to pack up to eight ports on a card serving distances of hundreds of kilometers.
"Coherent technology is one of the fundamental technologies of what I call the Optical Reboot: the optical network architecture transformation that will take place this decade," said Andrew Schmitt, optical analyst at market watcher Infonetics Research in a PMC statement.
The transceivers eliminate the need for signal filtering systems cost hundreds of dollars that would otherwise need to be installed and manually tuned as often as every 80 kilometers in a 40G optical network. Thanks to the on-chip DSP blocks, they also end the need for tunable dispersion compensators which sometimes required an entire line card.
PMC's Polo 40G uses DP-QPSK modulation and provides an SFI 5.1 client interface. It can also be used with CFP2 optical modules. The PM6373 Polo 40G will sample in the fall and be in production in early 2012 at prices to be determined.
Startup ClariPhy said it is sampling a similar device now that will be in production in the fall. The chip is already running in prototype systems, it said.
ClariPhy founder and CTO Norm Swenson said some carriers believe 40G coherent networks are the best route forward. The technique captures phase information that can be used to improve optical signals in a CMOS chip. Today's systems that use a direct detect approach that loses the phase data, forcing designers to use extra components and sometimes whole line cards to improve optical signal quality.