PORTLAND, Ore.—A new wafer pruning technique could save 15 percent in semiconductor chip manufacturing costs and increase profits per chip by as much as 12 percent, according to the Semiconductor Research Corp., which funded development of the technique at the University of California at Los Angeles (UCLA).
The new wafer pruning technique is currently being characterized by IBM Corp. for its 45-nanometer process, using on-wafer monitoring structures that can be probed during fabrication to spot bad wafers early-on.
The wafer pruning technique positions the test structures between die on a wafer, similar to the test structures installed there today to monitor process drift. By repurposing these test structures for pruning wafers—that is, rejecting wafers early in their fabrication by detecting errors in the test structures—an overall boost in yields should increase profits, which IBM is currently measuring.
"Wafer pruning ultimately leads to less expensive and higher performing electronics devices, especially if the pruning can be done during the early stages of manufacturing," said Puneet Gupta, an SRC alumni and professor of electrical engineering at UCLA. "Pruning is also especially useful in the early stages of yield ramp for a new chip."
Design dependent process monitoring spots bad wafers early-on by comparing design house timing and power models with measurements made on special test structures between die.
The design-dependent process installs easy-to-test structures which detect anomalies in capacitance, resistance and other telltale signs which indicate that nearby die are probably bad too. If enough errors are detected in early stages of processing a wafer, it can be rejected. By pruning bad wafers, there is a significant saving in the cost of additional processing steps, such as the complex metallization layers that are usually left for last.
Gupta estimates that 70 percent of failed chips can be pruned using test structures to detect a wide range of power level and performance variations. Simple test structures positioned between die enable the spotting of detects early-on, before dicing and packaging, thus reducing the testing cost of detecting faults in finished chips too.
"Design-assisted manufacturing techniques like those developed by professor Gupta, leverage design information to reduce process control requirements, something all our members can benefit from," said Bill Joyner, SRC director of computer aided design and test. "Design-assisted manufacturing will also help our members with technology scaling."
IBM will be testing the SRC-inspired wafer pruning technique developed by Gupta by adding the necessary test structures between die on its 45-nm process, then performing the necessary testing during fabrication to prune potentially bad wafers. By keeping careful track of all metrics, IBM hopes to use its analytics to fully characterize the improved yields and cost savings that can be achieved using wafer pruning. Once the field testing results are in, the wafer pruning processes could be adopted by any SRC member company, including Advanced Micro Devices Inc., Freescale Semiconductor Inc., Globalfoundries Inc., IBM, Intel Corp. and Texas Instruments Inc.
Let's assume this pruning is only for new process development, not mature processes. In that early phases of new device development, fab wafer-lot starts are rationed as then are the sub-lot wafers per technology node split. Please name the group who would like to see the new device development wafers terminated mid-stream ...device engineers, yield enhancement, thin films, metalization, etch, clean-up, reliability. There is a wealth of information to be gathered from fully processed (but dead) wafers by various groups. Just because the transistors are dead does not mean the wafers are profitably terminated early. OTOH, I may have said too much to IBM...
I kind of have the same feeling, we've been doing M1 testing on devices for as long as I have been involved in semicon manufacturing (~15yrs). And yes, we use it to scrap wafers before going through the metal steps.
I too am lost on the many details this article omits! I agree with @ebmfuser, the methodology of using test structures in the street for yield prediction for ages now. The article doesn't how 'early' in the manufacturing process the wafers are going to be held for probing -at contact? Or, at M1 as @daleste suggested? Is the fabrication of interconnects (contact to M1) required for this IBM's 'pruning' process?
I must be missing something as well. Process Control Monitor Dropins (PCM's), either in the scribe streets or a device cell, have been used as parametric data generator and/or a yield predictor for decades - especially in the compound semiconductor world. Sounds to me like IBM is simply going back to the 'old ways' and trying to make it sound as if they just invented the concept.
I must be missing something here.. Current scribe grid test structures aren't used "just to measure process drift". Any self respecting company should have correlations to yield and identified key parametric structures for each product to enable data driven "pruning" decisions based on M1 data.
Notice that it is design dependendent and is pruning based on power levels and performance - in other words if the transistors aren't low power enough or fast enough to meet design requirments then it's not worth putting the metals on. This can address yield issues with new processes or pushing the envelope issues with new designs.
You can't test them until metal 1. That may be about half way thru the process, but the metal layers are more expensive and time consuming. This seems like a good idea for new evolving processes. Mature processes just don't make bad wafers.
I don't buy this manufacturing philosophy. If it makes financial sense to prune entire 300mm wafers mid-line, then they have significant internal process yield problems. Such wafers should be rare, rather than a cost saving opportunity. I don't know how many times I have heard product engineers telling us not to scrap known-dead split wafers so they could later pull parametric data off them at the end of the line. In fairness, I"d like to see the math that supports this approach.
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