SAN FRANCISCO—ASIC design and manufacturing services provider Open-Silicon Inc. Friday (May 27) claimed an industry first, announcing a money-back guarantee on design engineering schedules.
Under the new program, Open-Silicon (Milpitas, Calif.) will meet a customer's schedule, delivering a prototype on time, or refund the cost of the physical design engineering up to $500,000, the company said. The offer applies only to designs using process technologies, IP and packaging that Open-Silicon has experience with—designs at 28-nm or using exotic IP or packaging are not covered.
According to Naveed Sherwani, Open-Silicon's president and CEO, the company is offering the program for a limited time because it is confident in its ability to meet schedules and because although customers emphasize the importance of hitting market windows, they often make late changes to a design that cause schedules to slip.
"The main reason we are doing this is because we have learned something in the last eight years," Sherwani said. "The big way to make money is not to argue about the cost of NRE—that's small money compared to what Open-Silicon makes if the product hits the market at the right time. The purpose of this program is to cajole, push, encourage and do whatever is necessary to get our customers' products into the market on time, because they benefit and we benefit."
The "On Time, or On Us," program is set to run through December. Sherwani said Open-Silicon is offering it for a limited time to gauge customer interest. The program covers qualifying designs in 40- or 65-nm process technology. Uner the terms of this program, the originally quoted design non-recurring engineering charge will be refunded, up to $500,000. for programs that miss the committed development schedule for prototype delivery.
Sherwani said Open-Silicon tracks its on-time delivery rate and reports it internally every month. The company's goal is a predictability rate of 90 percent. Historically, Open-Silicon's predictability rate has varied from as low as 75 percent to a high of about 92 percent, and is currently hovering around 85 percent, he said. In cases when Open-Silicon fails to meet a schedule, the fault rests with customers about 90 percent of the time, according to Sherwani.
"The big debate I'd like to get started in the industry is: why our industry is not as predictable as other industries," Sherwani said. "People say our industry is maturing. In a mature industry, I think it becomes inherently predictable."
Sherwani compared ASIC design to the auto industry. Building a car is just as complicated as designing an ASIC, he said, yet when people go into a dealership and choose the make, model, color and accessories they want in their vehicle, they almost always get it on time. But in ASIC design, schedule slip is often more the rule than the exception, he said.
"It's because there is a commitment," Sherwani said. "I think we should make the commitment as well." Sherwani urged his colleagues in design, test and packaging to create similar programs.
I agree with most of the comments here that this is reflection of the confidence that the company has. Just wondering if this will inspire other companies to come-up with such innovative marketing tactics ?
Every year, auto industry is pumping out of car with a little bit of change from the last year, because they know a customer does not want to buy the 1 year old car with the same price. For a very new car, automaker prepares for many years from a part to assembly line.
A bit different from ASIC industry. ASIC/FPGA/System industry is usually run 6 month or 1 year to compete a new design. As tools and expertise are getting mature, a design phase may become shorter. More over, some of design cycle, particularly in a back-end cycles are almost one push-button style.
Why ASIC design process is delayed sometime is due to a complexity of verification. From what I read other engineers’ article and my experience, there is a bottleneck in verification process. The functional count multiplied by a clock speed is almost impossible to meet a time line. That is why any IP coming up, because it is not my bug, if IP works incorrectly.
I don’t want to argue with Sherwani’s sales pitch. I have to say this is very unrealistic sales talk to a hand-on verification engineer, while it is very attractive offer to Director or CFO level. If you get your money back for a slip of project schedule, it is the one I could bet my money on, regardless who they did it.
Truly a great offering from Open-Silicon, for the first time someone in the silicon asic industry has spoken like words, this also shows the confidence in his field when they give this kind of commitment.
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